Semiconductor device

Patent metadata

Field	Value
Publication number	US-10134838-B2
Application number	US-201715820053-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Dec 22, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A semiconductor device includes a substrate that includes active patterns extending in a second direction, a third device isolation layer disposed on an upper portion of the substrate that includes a PMOSFET region and an NMOSFET region, and a gate electrode that extends across the active patterns in a first direction that crosses the second direction. The active patterns extend across the PMOSFET region and the NMOSFET region. The third device isolation layer lies between the PMOSFET region and the NMOSFET region. The third device isolation layer comprises a first part that extends in the second direction and a second part that extends in a third direction that crosses the first and second directions. The second part has opposite sidewalls parallel to the third direction, in a plan view.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate that includes active patterns that extend in a second direction;
a third device isolation layer disposed on an upper portion of the substrate, the third device isolation layer defining a PMOSFET region and an NMOSFET region in the substrate; and
a gate electrode that extends across the active patterns in a first direction that crosses the second direction,
wherein the active patterns extend across the PMOSFET region and the NMOSFET region, and
wherein the third device isolation layer is disposed between the PMOSFET region and the NMOSFET region, the third device isolation layer comprising:
a first part that extends in the second direction; and
a second part that extends in a third direction that crosses the first and second directions, wherein the second part has opposite sidewalls parallel to the third direction, in a plan view.

2. The device of claim 1 , wherein the first part has a first width in a direction perpendicular to the second direction, and the second part has a second width in a direction perpendicular to the third direction,
wherein the first and second widths are substantially equal to each other.

3. The device of claim 1 , wherein the third device isolation layer further comprises a third part that extends in the second direction, wherein
the second part is interposed between the first and third parts, and
the number of the active patterns of the PMOSFET region adjacent to the first part differs from the number of the active patterns of the PMOSFET region adjacent to the third part.

4. The device of claim 1 , further comprising first device isolation layers disposed on the upper portion of the substrate that extend in the second direction,
wherein the first device isolation layers define the active patterns, and
wherein a depth of the third device isolation layer is greater than a depth of the first isolation layers.

5. The device of claim 4 , further comprising a second device isolation layer disposed on the upper portion of the substrate that separates the active patterns from each other in the second direction,
wherein the second device isolation layer extends in the first direction, and
wherein the depth of the third device isolation layer is greater than a depth of the second isolation layers.

6. The device of claim 5 , wherein
the second device isolation layer penetrates upper portions of the first device isolation layers, and
the depths of the first device isolation layers are greater than the depth of the second isolation layer.

7. The device of claim 4 , wherein an upper portion of each of the active patterns has a fin shape that protrudes between the first isolation layers.

8. The device of claim 1 , wherein the active patterns comprises a first active pattern adjacent to the second part of the third device isolation layer,
wherein the first active pattern has a first sidewall parallel to the third direction, in a plan view, the first sidewall of the first active pattern being vertically aligned with one of the opposite sidewalls of the second part.

9. The device of claim 8 , further comprising:
first device isolation layers that covers a second sidewall and a third sidewall of the first active pattern; and
a second device isolation layer that covers a fourth sidewall of the first active pattern, the fourth sidewall being opposite to the first sidewall,
wherein the second and third sidewalls of the first active pattern are parallel to the second direction, in a plan view,
wherein the fourth sidewall of the first active pattern is parallel to the first direction, in a plan view, and
wherein the first to third device isolation layers each have different depths.

10. The device of claim 1 , wherein an upper portion of each of the active patterns comprises:
a pair of source/drain regions on opposite sides of the gate electrode; and
a channel region between the source/drain regions.

11. A semiconductor device comprising:
a substrate that includes an active pattern that extends in a second direction; and
first device isolation layers and a third device isolation layer disposed on an upper portion of the substrate,
wherein
the active pattern comprises first to fourth sidewalls,
the second sidewall is opposite to the first sidewall, and the fourth sidewall is opposite to the third sidewall,
the first device isolation layers cover the first and second sidewalls of the active pattern,
the third device isolation layer covers the third sidewall of the active pattern,
the first and second sidewalls are parallel to the second direction, in a plan view,
the fourth sidewall is parallel to a first direction that crosses the second direction, in a plan view,
the third sidewall is parallel to a third direction that crosses the first and second directions, in a plan view, and
the third device isolation is deeper than the first device isolation layers.

12. The device of claim 11 , wherein an upper portion of the active pattern has a fin shape that protrudes between the third device isolation layer and the first device isolation layers.

13. The device of claim 11 , further comprising a second device isolation layer that covers the fourth sidewall of the active pattern,
wherein the first device isolation layers are deeper than the second device isolation layer.

14. The device of claim 11 , wherein
the substrate comprises a PMOSFET region and an NMOSFET region defined by the third device isolation layer,
the active pattern comprises a first active pattern on the PMOSFET region and a second active pattern on the NMOSFET region,
the third device isolation layer comprises a first part that extends in the third direction,
the third sidewall of the first active pattern is aligned with one of opposite sidewalls of the first part, and
the third sidewall of the second active pattern is aligned with the other of opposite sidewalls of the first part.

15. The device of claim 11 , wherein the third device isolation layer comprises a second part that extends in the third direction, a first part that extends in the second direction, and a third part that extends in the second direction, wherein
the second part is interposed between the first and third parts, and
the second part covers the third sidewall of the active pattern.

16. A semiconductor device comprising:
a substrate that includes active patterns that extend in a second direction;
first device isolation layers disposed on an upper portion of the substrate that extend in the second direction, wherein the first device isolation layers define the active patterns;
a second device isolation layer disposed on the upper portion of the substrate that separates the active patterns from each other in the second direction, wherein the second device isolation layer extends in a first direction that crosses the second direction; and
a third device isolation layer disposed on the upper portion of the substrate, wherein the third device isolation layer comprises:
a first part that extends in the second direction;
a second part that extends in a third direction that crosses the first and second directions, wherein the second part has opposite sidewalls parallel to the third direction, in a plan view, and
a third part that extends in the second direction, wherein the second part is interposed between the first and third parts.

17. The semiconductor device of claim 16 , wherein:
the third device isolation layer defines a PMOSFET region and an NMOSFET region in the substrate,
the active patter

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myoung-Ho
• Do Jung-Ho
• Yang Giyoung
• Lee Seungyoung

Classifications

• H01L21/823821

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic