Layout design system for generating layout design of semiconductor device

Patent metadata

Field	Value
Publication number	US-9659130-B2
Application number	US-201414521928-A
Country	US
Kind code	B2
Filing date	Oct 23, 2014
Priority date	Jan 22, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted.

First claim

What is claimed is:

1. A layout design system comprising:
a processor;
a storage module configured to store a standard cell design, the standard cell design including an active area and a normal gate area on the active area; and
a generation module,
the generation module being configured to receive the standard cell design,
the generation module being configured to adjust a width of an active cut design crossing the active area of the standard cell design,
the generation module being configured to output a chip design including a design element using the processor,
the design element including the active cut design having the width adjusted, and
the generation module being configured to adjust the width of the active cut design using a marker, wherein
the standard cell design includes a first standard cell design and a second standard cell design,
the first standard cell design includes a first active area extending in a first direction,
the second standard cell design includes a second active area extending in the first direction,
the first and second active areas are spaced apart from each other in the first direction,
the active cut design is between the first standard cell design and the second standard cell design,
the active cut design includes a first part spaced apart from a second part in the first direction,
the first part is one end of the active cut design facing the first active area,
the second part is an other end of the active cut design facing the second active area,
the marker includes a first marker and a second marker,
the generation module is configured to adjust a width of the first part of the active cut design in the first direction using the first marker, and
the generation module is configured to adjust a width of the second part of the active cut design in the first direction using the second marker,
the first marker is generated on a boundary between the first active area and the first part of the active cut design so as to overlap with the first active area and the first part of the active cut design, and
the second marker is generated on a boundary between the second active area and the second part of the active cut design so as to overlap with the second active area and the second part of the active cut design.

2. The layout design system of claim 1 , wherein
the first standard cell design further includes a first normal gate area on the first active area,
the first normal gate area extends in a second direction crossing the first direction, and
the generation module is configured to adjust a distance between the first normal gate area and the first part using the first marker.

3. The layout design system of claim 2 , wherein
the first standard cell design further includes a first dummy gate area on the first active area,
the first dummy gate area is spaced apart from the first normal gate area in the first direction,
the first dummy gate area is between the first normal gate area and the first part, and
the first marker does not overlap with the first dummy gate area.

4. The layout design system of claim 1 , wherein
the first standard cell design further includes a first active fm extending in the first direction on the first active area, and
the generation module is configured to adjust a length of the first active fin in the first direction using the first marker.

5. The layout design system of claim 4 , wherein the length of the first active fin in the first direction is equal to a length of the first active area in the first direction.

6. The layout design system of claim 1 , wherein the standard cell design further includes the design element.

7. The layout design system of claim 1 , wherein the generation module is configured to generate the design element.

8. A layout design system comprising:
a processor;
a storage module configured to store a plurality of standard cell designs and a plurality of candidate active cut designs,
the plurality of candidate active cut designs having different shapes,
each of the standard cell designs including an active area and a normal gate area on the active area;
a displacement module,
the displacement module being configured to place the plurality of standard cell designs using the processor according to a defined requirement received by the displacement module, and
the displacement module being configured to select one of the plurality of candidate active cut designs and to dispose the selected candidate active cut design between the plurality of standard cell designs; and
a generation module,
the generation module being configured to generate a chip design using an input generated from the displacement module,
the input including the selected one of the candidate active cut designs disposed between the plurality of standard cell designs, and
the generation module being configured to adjust a with of the selected one of the candidate active cut designs in response to the defined requirement so the chip design generated by the generation module includes the selected one of the candidate active cut designs having the width adjusted.

9. The layout design system of claim 8 , wherein
each one of the standard cell designs includes a first standard cell design and a second standard cell design,
the first standard cell design includes a first active area extending in a first direction,
the second standard cell design includes a second active area extending in the first direction,
the first and second active areas are spaced apart from each other in the first direction,
and the displacement module is configured to dispose the selected candidate active cut design between the first standard cell design and the second standard cell design.

10. The layout design system of claim 9 ,
wherein
the generation module is configured to generate a first marker and a second marker,
the first marker is on a boundary between the first standard cell design and the selected candidate active cut design, and
the second marker is on a boundary between the second standard cell design and the selected candidate active cut design.

11. The layout design system of claim 10 , wherein the displacement module and the generation module are stored in the storage module or stored in an other storage module separated from the storage module.

12. The layout design system of claim 10 , further comprising:
an integration module, wherein
the integration module is configured to implement the displacement module and the generation module.

13. A layout design system comprising:
a processor;
a storage module configured to store at least one standard cell design,
the standard cell design including at least one gate area on an active area; and
a generation module configured to generate a chip design including a design element using the processor by adjusting a width of an active cut design crossing the active area,
the design element including the active cut design having the width adjusted, wherein
the active area includes a first active area spaced apart in a first direction from a second active area,
the standard cell design includes the active cut design,
the active cut design is between the first and second active areas,
the active cut design includes a first part spaced apart in the first direction from a second part,
the generation module is configured to adjust the width of the active cut design by adjusting a width in the first direction of the first part using a first marker and adjusting a width in the first direction of the second part using a second marker,
the first marker overlaps a boundary between the first part and th

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jin-Tae
• Seo Jae-Woo

Classifications

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5068

  Physics · mapped topic

• G06F17/5072 Primary

  Physics · mapped topic

• G06F2119/02

  Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] · CPC title