Controller, semiconductor memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-9825651-B2
Application number	US-201514958449-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Jun 25, 2015
Publication date	Nov 21, 2017
Grant date	Nov 21, 2017

Abstract

An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size.

First claim

What is claimed is:

1. An operation method for a controller, comprising:
a first step of generating plurality of internal codewords each including an ECC unit data and an internal parity code by performing ECC encoding operation to an input data;
a second step of updating an external parity code based on the ECC unit data, which is included in a first internal codeword currently generated, and the ECC unit data, which is included in a second internal codeword previously generated and buffered,
wherein, the plurality of internal codewords include the first internal codeword and the second internal codeword,
wherein, the first and the second steps are repeated; and
a third step of storing in a semiconductor memory device the plurality of internal codewords and the updated external parity code, which are generated through the repetition of the first and second steps, by a unit of predetermined storage size,
wherein, when a program operation normally ends during the repetition of the first and second steps, the third step further adds a dummy code having a value representing a erase-state memory cell in the unit of predetermined storage size, which is not completely filled with the plurality of internal codewords and the external parity code at the end of the program operation.

2. The operation method of claim 1 , wherein the ECC encoding operation is performed based on a concatenated Bose-Chaudhuri-Hocquenghem (CBCH) code.

3. The operation method of claim 1 , wherein the third step stores the plurality of internal codewords in the semiconductor memory device through interleaving.

4. An operation method for a controller, comprising:
a first step of performing a first ECC decoding to a readout codeword provided from a semiconductor memory device, and generating a plurality of internal data each corresponding to ECC unit data included in the readout codeword;
a second step of generating read unit data by performing zero padding to the internal data and an external parity code for all of the ECC unit data upon detection of one or more dummy codes having values representing one or more erase-state memory cells; and
a third step of performing a second ECC decoding operation to the read unit data based on the external parity code,
wherein the readout codeword includes a plurality of internal codewords each having the ECC unit data, and the external parity code,
wherein the readout codeword further includes the dummy codes,
wherein the readout codeword includes the dummy code subsequent to the plurality of internal codewords, and
wherein the second step generates the read unit data by performing the zero padding operation to the read unit data, which is not completely filled with the internal data and the external parity code.

5. The operation method of claim 4 , wherein one or more of the plurality of internal data fail in the first ECC decoding operation.

6. The operation method of claim 4 , wherein one or more of the first and second ECC decoding operations are performed based on a concatenated Bose-Chaudhuri-Hocquenghem (CBCH) code.

7. A controller comprising:
an internal encoder suitable for sequentially generating a plurality of internal codewords each including an ECC unit data and an internal parity code by performing ECC encoding operation to an input data, and storing the plurality of internal codewords; and
an external encoder suitable for buffering the ECC unit data, and updating an external parity information based on the ECC unit data, which is included in a first internal codeword currently generated, and the ECC unit data, which is included in a second internal codeword previously generated and buffered,
wherein, the plurality of internal codewords include the first internal codeword and the second internal codeword, and
wherein, when a program operation normally ends in the course of generating and storing of the plurality of internal codewords, the controller stores so-far generated the plurality of internal codewords, so-far updated external parity information and dummy codes having values representing erase-state memory cells in the semiconductor memory device by a unit of predetermined storage size.

8. The controller of claim 7 , the ECC encoding operation is performed based on a concatenated Bose-Chaudhuri-Hocquenghem (CBCH) code.

9. The controller of claim 7 , wherein the controller stores the plurality of internal codewords in the semiconductor memory device through interleaving.

10. A controller comprising:
an internal decoder suitable for performing a first ECC decoding to a readout codeword provided from a semiconductor memory device, and generating a plurality of internal data each corresponding to ECC unit data included in the readout codeword;
a detector suitable for generating a detection signal by detecting one or more dummy codes having values representing one or more erase-state memory cells;
a formatter suitable for generating read unit data by performing zero padding to the internal data and an external parity code for all of the ECC unit data in response to the detection signal; and
an external decoder suitable for performing a second ECC decoding operation to the read unit data based on the external parity code,
wherein the readout codeword includes a plurality of internal codewords each having the ECC unit data, and the external parity code,
wherein the readout codeword further includes the dummy codes,
wherein the readout codeword includes the dummy code subsequent to the plurality of internal codewords, and
wherein the formatter generates the read unit data by performing the zero padding operation to the read unit data, which is not completely filled with the internal data and the external parity code.

11. The controller of claim 10 , wherein the detector is activated when one or more among the plurality of internal data fails in the first ECC decoding operation.

Assignees

• Sk Hynix Inc

Inventors

• Rho Jun-Rye
• Cho Sung-Gun

Classifications

• H03M13/1102

  Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes · CPC title

• H03M13/6356

  by repetition or insertion of dummy data, i.e. rate reduction · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• H03M13/2957

  Turbo codes and decoding · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title