Protecting an ECC location when transmitting correction data across a memory link

Patent metadata

Field	Value
Publication number	US-10140175-B2
Application number	US-201615081460-A
Country	US
Kind code	B2
Filing date	Mar 25, 2016
Priority date	Nov 20, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A memory sub-system may include a memory controller having error correction code (ECC) encoder/decoder logic. The memory controller may be configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation. The memory controller may also be configured to protect at least a location of the link ECC parity bits during the mask write operation.

First claim

What is claimed is:

1. A method of link error correction and protection in a low power memory sub-system, comprising:
embedding link error correction code (ECC) parity bits in unused data mask bits and/or in a mask write data during a mask write operation; and
protecting at least a location of the link ECC parity bits in either the unused data mask bits or the mask write data against a link error during the mask write operation by identifying the unused data mask bits or the mask write data during the mask write operation as the location of the link ECC parity bits.

2. The method of claim 1 , in which protecting at least the location of the link ECC parity bits comprises transmitting data mask ECC parity bits during the mask write operation to protect at least a first asserted data mask bit identifying the link ECC parity bits embedded in a corresponding mask write data byte.

3. The method of claim 2 , further comprising transmitting an ECC location code of the link ECC parity bits within a predetermined burst length of write data during the mask write operation.

4. The method of claim 3 , further comprising transmitting the data mask ECC parity bits and the ECC location code of the link ECC parity bits over a command/address bus during the mask write operation.

5. The method of claim 1 , in which embedding during the mask write operation comprises:
determining whether a predetermined burst length of write data includes an asserted data mask bit;
embedding the link ECC parity bits in a first mask write data byte corresponding to the first asserted data mask bit and within the first asserted data mask bit; and
otherwise, embedding the link ECC parity bits in the unused data mask bits.

6. The method of claim 1 , in which protecting at least the location of the link ECC parity bits comprises transmitting a beat location code indicating a block location of the link ECC parity bits within a predetermined burst length of write data during the mask write operation.

7. The method of claim 6 , further comprising transmitting a block location code indicating whether the link ECC parity bits are embedded in a data portion or the data mask portion of the predetermined burst length of write data.

8. The method of claim 7 , further comprising transmitting the beat location code and the block location code over a command/address bus during the mask write operation.

9. The method of claim 1 , further comprising receiving timing information for capture of read data during a read operation.

10. The method of claim 1 , further comprising integrating the low power memory sub-system into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, a fixed location data unit, a server computing system and/or a vehicle control system.

11. A memory sub-system, comprising:
a memory controller having error correction code (ECC) encoder/decoder logic, the memory controller configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation and configured to protect at least a location of the link ECC parity bits in either the unused data mask bits or the mask write data against a link error during the mask write operation by identifying the unused data mask bits or the mask write data during the mask write operation as the location of the link ECC parity bits.

12. The memory sub-system of claim 11 , in which the memory controller is further configured to transmit data mask ECC parity bits during the mask write operation to protect at least a first asserted data mask bit identifying the link ECC parity bits embedded in a corresponding mask write data byte and to transmit an ECC location code of the link ECC parity bits within a predetermined burst length of write data during the mask write operation.

13. The memory sub-system of claim 12 , in which the memory controller is further configured to transmit the data mask ECC parity bits and the ECC location code of the link ECC parity bits over a command/address bus during the mask write operation.

14. The memory sub-system of claim 11 , in which the memory controller is further configured to transmit a beat location code indicating a block location of the link ECC parity bits within a predetermined burst length of write data during the mask write operation and to transmit a block location code indicating whether the link ECC parity bits are embedded in a data portion or the data mask portion of the predetermined burst length of write data.

15. The memory sub-system of claim 14 , in which the memory controller is further configured to transmit the beat location code and the block location code over a command/address bus during the mask write operation.

16. The memory sub-system of claim 15 , in which the memory controller is further configured to determine whether the predetermined burst length of write data includes an asserted data mask bit, to embed the link ECC parity bits in a first mask write data byte corresponding to the first asserted data mask bit and within the first asserted data mask bit and to otherwise embed the link ECC parity bits in the unused data mask bits.

17. The memory sub-system of claim 11 , in which the memory controller is further configured to receive timing information for improving capture of read data during a read operation.

18. The memory sub-system of claim 11 integrated into a mobile phone, a set top box, a music player, a video player, an entertainment unit, a navigation device, a computer, a hand-held personal communication systems (PCS) unit, a portable data unit, a fixed location data unit, a server computing system and/or a vehicle control system.

19. A memory sub-system, comprising:
a memory controller having error correction code (ECC) encoder/decoder logic configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation and configured to protect at least a location of the link ECC parity bits in either the unused data mask bits or the mask write data against a link error during the mask write operation by identifying the unused data mask bits or the mask write data during the mask write operation as the location of the link ECC parity bits; and
a memory device coupled to the memory controller via at least a data bus, comprising:
link ECC decoder and correction logic in a write path and configured for detection and correction of link errors during transmission of write data over the data bus; and
memory ECC encoder logic in the write path and configured for memory protection of the write data during storage within a memory array according to memory ECC parity bits.

20. The memory sub-system of claim 19 , in which the memory controller is further configured to transmit data mask ECC parity bits during the mask write operation to protect at least a first asserted data mask bit identifying the link ECC parity bits embedded in a corresponding mask write data byte and to transmit an ECC location code of the link ECC parity bits within a predetermined burst length of write data during the mask write operation.

21. The memory sub-system of claim 20 , in which the memory controller is further configured to transmit the data mask ECC parity bits and the ECC location code of the link ECC parity bits over a command/address bus during the mask write operation.

22. The memory sub-system

Assignees

• Qualcomm Inc

Inventors

• West David Ian
• Suh Jungwon

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title