Capacitance detection circuit and method, and electronic device

US12224745B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12224745-B2
Application numberUS-202217944061-A
CountryUS
Kind codeB2
Filing dateSep 13, 2022
Priority dateJul 21, 2020
Publication dateFeb 11, 2025
Grant dateFeb 11, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

This application provides a capacitance detection circuit for detecting capacitance of a capacitor element within a capacitor array. The circuit includes a capacitance detection module for detecting a first capacitance of a first capacitor set, a second capacitance of a second capacitor set, and a third capacitance of the third capacitor set, the first capacitor set comprising the capacitor element and a row capacitor element in the same row of the capacitor array as the capacitor element, the second capacitor set comprising the capacitor element and a column capacitor element in the same column of the capacitor array as the capacitor element, the third capacitor set comprising the row capacitor element and the column capacitor element; and a processing module, configured to obtain the capacitance of the capacitor element according to the first capacitance, the second capacitance and the third capacitance.

First claim

Opening claim text (preview).

What is claimed is: 1. A circuit for detecting capacitance of a capacitor element within a capacitor array, the circuit comprising: a capacitance detection module, configured to detect a first capacitance of a first capacitor set, a second capacitance of a second capacitor set, and a third capacitance of a third capacitor set, the first capacitor set comprising the capacitor element and a row capacitor element in a same row of the capacitor array as the capacitor element, the second capacitor set comprising the capacitor element and a column capacitor element in a same column of the capacitor array as the capacitor element, the third capacitor set comprising the row capacitor element and the column capacitor element; and a processing module, configured to obtain the capacitance of the capacitor element according to the first capacitance, the second capacitance and the third capacitance by: determining the capacitance of the capacitor element by the formula: C t =(C 1 +C 2 −C 3 )/2, wherein C t is the capacitance of the capacitor element, C 1 is the first capacitance, C 2 is the second capacitance, and C 3 is the third capacitance. 2. The circuit according to claim 1 , further comprising a switching module, wherein the switching module is configured to connect the capacitance detection module to the first capacitor set, the second capacitor set and the third capacitor set, respectively. 3. The circuit according to claim 2 , wherein the switching module comprises a first switch and a second switch, and both the first switch and the second switch each comprise a first contact, a second contact, and a third contact, wherein the first contact of the first switch and the first contact of the second switch are both connected to the capacitance detection module; the second contact of the first switch and the second contact of the second switch are both grounded; the third contact of the first switch is connected to a first terminal of the capacitor element, and grounded through the row capacitor element; and the third contact of the second switch is connected to a second terminal of the capacitor element, and grounded through the column capacitor element. 4. The circuit according to claim 3 , wherein the processing module is configured to control the connection of the contacts in the first switch and the second switch to form three connection states, wherein in a first connection state of the three connection states, the capacitance detection module is respectively connected to one terminal of the capacitor element and the row capacitor element, and the other terminal of the capacitor element and the row capacitor element is grounded; and both terminals of the column capacitor element are grounded; in a second connection state of the three connection states, the capacitance detection module is respectively connected to one terminal of the capacitor element and the column capacitor element, and the other terminal of the capacitor element and the column capacitor element is grounded; and both terminals of the row capacitor element are grounded; and in a third connection state of the three connection states, the capacitance detection module is respectively connected to one terminal of the row capacitor element and the column capacitor element, and the other terminal of the capacitor row element and the column capacitor element is grounded; and both terminals of the capacitor element are connected to the capacitance detection module. 5. The circuit according to claim 1 , further comprising: a switch module, wherein the capacitance detection module is configured to be connected to the capacitor array through the switch module; and the processing module is connected to the switch module, and configured to determine the capacitor element, and control the switch module to connect the capacitance detection module to the capacitor element. 6. The circuit according to claim 5 , wherein the switch module comprises a plurality of row switches and a plurality of column switches, wherein each of the capacitor elements corresponds to one of the column switches and one of the row switches, and the processing module is configured to determine a target row switch and a target column switch corresponding to the capacitor element; and connect the target row switch and the target column switch to the capacitance detection module, ground other row switches than the target row switch in the plurality of row switches, and ground other column switches than the target column switch in the plurality of column switches. 7. The circuit according to claim 6 , wherein each of the row switches and each of the column switches comprise a first connection terminal, wherein the first terminal of each of the capacitor elements is connected to the first connection terminal of one of the column switches, and the second terminal of each of the capacitor elements is connected to the first connection terminal of one of the row switches; and the processing module is further configured to connect the first connection terminal of the target row switch and the first connection terminal of the target column switch to the capacitance detection module, ground the first connection terminals of other row switches than the target row switch in the plurality of row switches, and ground the first connection terminals of other column switches than the target column switch in the plurality of column switches. 8. The circuit according to claim 7 , wherein each of the row switches and each of the column switches further comprises a second connection terminal and a third connection terminal, wherein the second connection terminals of each of the row switches and each of the column switches are grounded, and the third connection terminals of each of the row switches and each of the column switches are connected to the capacitance detection module; and the processing module is further configured to: connect the first connection terminal to the third connection terminal of the target column switch, and disconnect the first connection terminal from the second connection terminal; connect the first connection terminal to the third connection terminal of the target row switch, and disconnect the first connection terminal from the second connection terminal; connect the first connection terminals to the second connection terminals of other row switches than the target row switch in the plurality of row switches, and disconnect the first connection terminals from the third connection terminal; and connect the first connection terminals to the second connection terminals of other column switches than the target column switch in the plurality of column switches, and disconnect the first connection terminals from the third connection terminal. 9. The circuit according to claim 1 , wherein the processing module is further configured to determine a capacitor element following the capacitor element as a newly capacitor element according to a preset detection sequence, and inform the capacitance detection module of the capacitor element; and the capacitance detection module is further configured to implement the operation of detecting the first capacitance, the second capacitance and the third capacitance and subsequent operations on the newly capacitor element, until all capacitor elements that require the detection of capacitance are detected according to the preset detection sequence. 10. An electronic device, comprising the capacitance detection circuit according to claim 1 , the electronic device being provided with an electronic skin including the capacitor array on a surface. 11. The electronic device according to claim 10 , wherein the electronic device

Assignees

Inventors

Classifications

  • Switched capacitor · CPC title

  • for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

  • Measuring capacitance (capacitive sensors G01D5/24) · CPC title

  • Tactile sensors (in general G01L5/16, G01L5/22) · CPC title

  • using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

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What does patent US12224745B2 cover?
This application provides a capacitance detection circuit for detecting capacitance of a capacitor element within a capacitor array. The circuit includes a capacitance detection module for detecting a first capacitance of a first capacitor set, a second capacitance of a second capacitor set, and a third capacitance of the third capacitor set, the first capacitor set comprising the capacitor ele…
Who is the assignee on this patent?
Tencent Tech Shenzhen Co Ltd
What technology area does this patent fall under?
Primary CPC classification H03K17/975. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Feb 11 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).