Capacitance detection circuit, capacitance detection method, touch chip, and electronic device

Patent metadata

Field	Value
Publication number	US-11206019-B2
Application number	US-202017060028-A
Country	US
Kind code	B2
Filing date	Sep 30, 2020
Priority date	May 28, 2019
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

The present disclosure relates to the field of touch technologies, and in particular, to a capacitance detection circuit, a capacitance detection method, a touch chip, and an electronic device. The capacitance detection circuit includes: a control module, a charge transfer module, a processing module, a drive module, and a cancellation module. The control module is configured to control the drive module to charge a capacitor to be detected. The cancellation module is configured to perform M times of charge cancellations on the capacitor to be detected. The charge transfer module is configured to convert a charge of the capacitor to be detected, subject to the M times of charge cancellations, to generate an output voltage. The processing module is configured to determine, according to the output voltage, a capacitance variation of the capacitor to be detected.

First claim

What is claimed is:

1. A capacitance detection circuit, comprising: a control module, a charge transfer module, a processing module, a drive module, and a cancellation module; wherein the cancellation module includes a cancellation capacitor, a second switch unit, and a third switch unit; the second switch unit is connected to one end of the cancellation capacitor, and the third switch unit is connected to the other end of the cancellation capacitor;
wherein the control module is configured to control the drive module to charge a capacitor to be detected,
the control module is further configured to control the second switch unit and the third switch unit to be in a first turned-on state, so that the cancellation module charges the cancellation capacitor,
the control module is further configured to control the second switch unit and the third switch unit to be in a second turned-on state, so that the cancellation capacitor performs a charge cancellation on the capacitor to be detected,
the control module is further configured to control the second switch unit and the third switch unit to switch back and forth between the first turned-on state and the second turned-on state for M times, so that the cancellation capacitor performs charge cancellations on the capacitor to be detected M times,
the charge transfer module is configured to convert a charge of the capacitor to be detected, subject to the M times of charge cancellations, to generate an output voltage, and
the processing module is configured to determine, according to the output voltage, a capacitance variation of the capacitor to be detected.

2. The circuit according to claim 1 , wherein the drive module comprises a first switch unit, and the control module is further configured to control the first switch unit to be in a turned-on state, so that the drive module charges the capacitor to be detected.

3. The circuit according to claim 2 , wherein when the first switch unit is in the turned-on state, a first end of the capacitor to be detected is electrically connected to a first voltage, and a second end of the capacitor to be detected is electrically connected to a second voltage, the first voltage being greater than the second voltage.

4. The circuit according to claim 3 , wherein the first voltage is provided by a positive voltage source, and the second voltage is a ground voltage.

5. The circuit according to claim 1 , wherein when the second switch unit and the third switch unit are in the first turned-on state, a first end of the cancellation capacitor is electrically connected to a third voltage through the second switch unit, and a second end of the cancellation capacitor is electrically connected to a fourth voltage through the third switch unit, the fourth voltage being greater than the third voltage; and when the second switch unit and the third switch unit are in the second turned-on state, the first end of the cancellation capacitor is electrically connected to the first end of the capacitor to be detected, and the second end of the cancellation capacitor is electrically connected to a fifth voltage, the fifth voltage being less than the second voltage electrically connected to the second end of the capacitor to be detected.

6. The circuit according to claim 1 , wherein when the second switch unit and the third switch unit are in the first turned-on state, a first end of the cancellation capacitor is electrically connected to a third voltage through the second switch unit, and a second end of the cancellation capacitor is electrically connected to a fourth voltage through the third switch unit, the fourth voltage being greater than the third voltage; and
when the second switch unit and the third switch unit are in the second turned-on state, the first end of the cancellation capacitor is electrically connected to the first end of the capacitor to be detected, and the second end of the cancellation capacitor is electrically connected to a sixth voltage, the sixth voltage being equal to the second voltage electrically connected to the second end of the capacitor to be detected.

7. The circuit according to claim 1 , wherein the cancellation module comprises a cancellation capacitor, a second switch unit, and performing M times of charge cancellations on the capacitor to be detected comprises that:
controlling, by the control module, the second switch unit to be in a first turned-on state, so that the cancellation module charges the cancellation capacitor;
controlling, by the control module, the second switch unit to be in a second turned-on state, so that the cancellation capacitor performs a charge cancellation on the capacitor to be detected; and
controlling, by the control module, the second switch unit to switch between the first turned-on state and the second turned-on state back and forth for M times, so that the cancellation capacitor performs the M times of charge cancellations on the capacitor to be detected.

8. The circuit according to claim 7 , wherein when the second switch unit is in the first turned-on state, a first end of the cancellation capacitor is electrically connected to a seventh voltage through the second switch unit, and a second end of the cancellation capacitor is electrically connected to an eighth voltage, the seventh voltage being less than the eighth voltage; and
when the second switch unit is in the second turned-on state, the first end of the cancellation capacitor is electrically connected to the first end of the capacitor to be detected, and the second end of the cancellation capacitor is electrically connected to the eighth voltage, the eighth voltage being equal to the second voltage electrically connected to the second end of the capacitor to be detected.

9. The circuit according to claim 7 , wherein when the second switch unit is in the first turned-on state, a first end of the cancellation capacitor is electrically connected to a ninth voltage through the second switch unit, and a second end of the cancellation capacitor is electrically connected to a tenth voltage, the ninth voltage being equal to the tenth voltage; and
when the second switch unit is in the second turned-on state, the first end of the cancellation capacitor is electrically connected to the first end of the capacitor to be detected, and the second end of the cancellation capacitor is electrically connected to an eighth voltage, the eighth voltage being equal to the second voltage electrically connected to the second end of the capacitor to be detected.

10. The circuit according to claim 1 , wherein a capacitance value of the cancellation capacitor and a value of M are related to a value of the capacitor to be detected, so that the cancellation capacitor performs the M times of charge cancellations on the capacitor to be detected.

11. The circuit according to claim 2 , wherein a capacitance value of the cancellation capacitor and a value of M are related to a value of the capacitor to be detected, so that the cancellation capacitor performs the M times of charge cancellations on the capacitor to be detected.

12. The circuit according to claim 3 , wherein a capacitance value of the cancellation capacitor and a value of M are related to a value of the capacitor to be detected, so that the cancellation capacitor performs the M times of charge cancellations on the capacitor to be detected.

13. The circuit according to claim 10 , wherein the capacitance value of the cancellation capacitor is inversely proportional to the value of M, and a larger value of M indicates a smaller capacitance value of the cancellation capacitor.

14. The circuit according to claim 1 , further com

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Jiang Hong

Classifications

• G06F3/0418

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0446

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• H03K2217/96074

  Switched capacitor · CPC title

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title