Circuit, touch chip, and electronic device for capacitance detection

Patent metadata

Field	Value
Publication number	US-10990230-B2
Application number	US-201916664889-A
Country	US
Kind code	B2
Filing date	Oct 27, 2019
Priority date	Sep 7, 2018
Publication date	Apr 27, 2021
Grant date	Apr 27, 2021

Abstract

Embodiments of the present disclosure provide a circuit, touch chip, and electronic device for capacitance detection, the circuit for capacitance detection comprising: a control module, a charge transfer module, a processing module, a driving module, and an offsetting module, the control module being configured to charge a detection capacitor by controlling the driving module, the offsetting module being configured to charge an offset capacitor, and control the offset capacitor to perform charge offsetting on the detection capacitor; the charge transfer module being configured to convert charge of the detection capacitor after the charge offsetting to generate an output voltage; and the processing module being configured to determine, based on the output voltage, a capacitance variation of the detection capacitor before and after the detection capacitor is affected by an external electric field.

First claim

What is claimed is:

1. A circuit for capacitance detection, comprising: a control module, a charge transfer module, a processing module, a driving module, and an offsetting module,
the control module being configured to: control the driving module to positively charge a detection capacitor, and control the offsetting module to negatively charge an offset capacitor in a same time interval, control the charged offset capacitor to perform charge offsetting on the charged detection capacitor to offset a base capacitance of the detection capacitor, and control the charge transfer module to convert charge of the detection capacitor after the charge offsetting to generate an output voltage; and
the processing module being configured to determine, based on the output voltage, a capacitance variation of the detection capacitor before and after the detection capacitor is affected by an external electric field;
wherein the offsetting module comprises a second switching unit and a third switching unit, the control module is further configured to control the second switching unit and the third switching unit to be in a first closed state and form a charging branch circuit, such that the offsetting module negatively charges the offset capacitor; and the control module is further configured to control the second switching unit and the third switching unit to be in a second closed state and form an offsetting branch circuit, such that the charged offset capacitor performs charge offsetting on the charged detection capacitor.

2. The circuit according to claim 1 , wherein the driving module comprises a first switching unit, and the control module is further configured to control the first switching unit to be in a closed state, such that the driving module positively charges the detection capacitor.

3. The circuit according to claim 2 , wherein the circuit further comprises a fourth switching unit, and the control module is further configured to control the fourth switching unit to be in a closed state, such that the charge transfer module is electrically connected to the detection capacitor, to convert the charge of the detection capacitor after the charge offsetting to generate the output voltage.

4. The circuit according to claim 2 , wherein when the first switching unit is in the closed state, a first terminal of the detection capacitor is electrically connected to a first voltage (VCC), a second terminal of the detection capacitor is electrically connected to a second voltage (GND), and the first voltage is higher than the second voltage.

5. The circuit according to claim 4 , wherein the circuit further comprises a fourth switching unit, and the control module is further configured to control the fourth switching unit to be in a closed state, such that the charge transfer module is electrically connected to the detection capacitor, to convert the charge of the detection capacitor after the charge offsetting to generate the output voltage.

6. The circuit according to claim 1 , wherein when the second switching unit and the third switching unit are in the first closed state, a first terminal of the offset capacitor is electrically connected to a third voltage (−VCC) via the second switching unit, a second terminal of the offset capacitor is electrically connected to a fourth voltage (VCC) via the third switching unit, and the fourth voltage is higher than the third voltage.

7. The circuit according to claim 1 , wherein when the second switching unit and the third switching unit are in the second closed state, a first terminal of the offset capacitor is electrically connected to a first terminal of the detection capacitor, a second terminal of the offset capacitor is electrically connected to a fifth voltage (−VCC), and the fifth voltage is lower than a second voltage (GND) electrically connected to the second terminal of the detection capacitor.

8. The circuit according to claim 1 , wherein when the second switching unit and the third switching unit are in the second closed state, a first terminal of the offset capacitor is electrically connected to a first terminal of the detection capacitor, a second terminal of the offset capacitor is electrically connected to a sixth voltage (GND), and the sixth voltage is equal to a second voltage (GND) electrically connected to the second terminal of the detection capacitor.

9. The circuit according to claim 1 , wherein the circuit further comprises a fourth switching unit, and the control module is further configured to control the fourth switching unit to be in a closed state, such that the charge transfer module is electrically connected to the detection capacitor, to convert the charge of the detection capacitor after the charge offsetting to generate the output voltage.

10. The circuit according to claim 1 , wherein the offsetting module comprises a second switching unit, the control module is further configured to control the second switching unit to be in a first closed state and form a charging branch circuit, such that the offsetting module negatively charges the offset capacitor; and the control module is further configured to control the second switching unit to be in a second closed state and form an offsetting branch circuit, such that the charged offset capacitor performs charge offsetting on the charged detection capacitor.

11. The circuit according to claim 10 , wherein when the second switching unit is in the first closed state, a first terminal of the offset capacitor is electrically connected to a third voltage (−VCC) via the second switching unit, a second terminal of the offset capacitor is electrically connected to a sixth voltage (GND), and the sixth voltage is higher than the third voltage.

12. The circuit according to claim 10 , wherein when the second switching unit is in the second closed state, a first terminal of the offset capacitor is electrically connected to a first terminal of the detection capacitor, a second terminal of the offset capacitor is electrically connected to a sixth voltage (GND), and the sixth voltage is equal to a second voltage (GND) electrically connected to the second terminal of the detection capacitor.

13. The circuit according to claim 1 , wherein the circuit further comprises a fourth switching unit, and the control module is further configured to control the fourth switching unit to be in a closed state, such that the charge transfer module is electrically connected to the detection capacitor, to convert the charge of the detection capacitor after the charge offsetting to generate the output voltage.

14. The circuit according to claim 13 , wherein when there are at least two detection capacitors, then each of the detection capacitors is equipped with one driving module and one offsetting module.

15. A touch chip, comprising a circuit for capacitance detection, the circuit comprising: a control module, a charge transfer module, a processing module, a driving module, and an offsetting module, the control module being configured to: control the driving module to positively charge a detection capacitor, and control the offsetting module to negatively charge an offset capacitor in a same time interval, control the charged offset capacitor to perform charge offsetting on the charged detection capacitor to offset a base capacitance of the detection capacitor, and control the charge transfer module to convert charge of the detection capacitor after the charge offsetting on the charged detection capacitor to generate an output voltage; and
the processing module being configured to determine, based on the output voltage, a capacitance variation of the detection capacit

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Jiang Hong
• Tang Zhi

Classifications

• G06F3/0416

  Control or interface arrangements specially adapted for digitisers · CPC title

• G01R27/2605

  Measuring capacitance (capacitive sensors G01D5/24) · CPC title

• G06F3/0418

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title

• G06F3/0446

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title