Devices having a semiconductor material that is semimetal in bulk and methods of forming the same

Patent metadata

Field	Value
Publication number	US-10461179-B2
Application number	US-201815905978-A
Country	US
Kind code	B2
Filing date	Feb 27, 2018
Priority date	Mar 13, 2015
Publication date	Oct 29, 2019
Grant date	Oct 29, 2019

Abstract

Devices, and methods of forming such devices, having a material that is semimetal when in bulk but is a semiconductor in the devices are described. An example structure includes a substrate, a first source/drain contact region, a channel structure, a gate dielectric, a gate electrode, and a second source/drain contact region. The substrate has an upper surface. The channel structure is connected to and over the first source/drain contact region, and the channel structure is over the upper surface of the substrate. The channel structure has a sidewall that extends above the first source/drain contact region. The channel structure comprises a bismuth-containing semiconductor material. The gate dielectric is along the sidewall of the channel structure. The gate electrode is along the gate dielectric. The second source/drain contact region is connected to and over the channel structure.

First claim

What is claimed is:

1. A method comprising:
forming an isolation region in a substrate, wherein the isolation region is between a first and second region of the substrate, and wherein at least a portion of the isolation region is configured to extend from a top surface of the substrate;
forming a first highly doped source/drain contact region in the first region of the substrate and a second highly doped source/drain contact region in the second region of the substrate;
forming a first gate electrode over the first highly doped source/drain contact region;
forming a second gate electrode over the second highly doped source/drain contact region;
forming a first opening through the first gate electrode and to the first highly doped source/drain contact region;
forming a second opening through the second gate electrode and to the second highly doped source/drain contact region;
depositing a first bismuth-containing semiconductor material in the first opening to form a first bismuth-containing channel structure, the first bismuth-containing channel structure being connected to the first highly doped source/drain contact region;
depositing a second bismuth-containing semiconductor material in the second opening to form a second bismuth-containing channel structure, the second bismuth-containing channel structure being connected to the second highly doped source/drain contact region;
forming a third source/drain contact region over and connected to the first bismuth-containing channel structure;
forming a fourth source/drain contact region over and connected to the second bismuth-containing channel structure;
forming a dielectric layer over the third source/drain contact region and the fourth source/drain contact region; and
crystallizing the first and second bismuth-containing semiconductor materials, the crystallizing comprising performing an anneal.

2. The method of claim 1 , wherein the first bismuth-containing semiconductor material is doped with an n-type dopant.

3. The method of claim 1 , wherein the second bismuth-containing semiconductor material is doped with a p-type dopant.

4. The method of claim 1 , wherein a cross section of the first bismuth-containing channel structure has a largest dimension 53 nm or less, and a cross section of the second bismuth-containing channel structure has a largest dimension 53 nm or less.

5. The method of claim 1 further comprising:
forming a first contact electrically coupled to the first highly doped source/drain contact region;
forming a second contact electrically coupled to the first gate electrode;
forming a third contact electrically coupled to the third source/drain contact region;
forming a fourth contact electrically coupled to the second highly doped source/drain contact region;
forming a fifth contact electrically coupled to the second gate electrode; and
forming a sixth contact electrically coupled to the fourth source/drain contact region.

6. The method of claim 1 , wherein the forming the first and second highly doped source/drain contact regions comprises:
forming a first mask on the second region of the substrate;
implanting a first dopant in the first region of the substrate to form a first doped well;
implanting a second dopant in the first doped well to form a first doped region;
removing the first mask from the second region of the substrate;
forming a second mask on the first region of the substrate;
implanting a third dopant in the second region of the substrate to form a second doped well;
implanting a fourth dopant in the second doped well to form a second doped region; and
removing the second mask from the first region of the substrate.

7. The method of claim 6 , wherein the first and fourth dopants are p-type dopants and wherein the second and third dopants are n-type dopants.

8. The method of claim 1 , wherein, after crystallizing, the first bismuth-containing channel structure and the second bismuth-containing channel structure each comprise a monocrystalline bismuth-containing material.

9. The method of claim 1 , wherein the forming a first and second highly doped source/drain contact regions comprises:
recessing the substrate in the first region and the second region;
forming a first mask on the second region of the substrate;
epitaxially growing a p-doped epitaxial layer on the substrate and in the first region of the substrate;
epitaxially growing an n+-doped epitaxial layer on the p-doped epitaxial layer and in the first region of the substrate;
removing the first mask from the second region of the substrate;
forming a second mask on the first region of the substrate;
epitaxially growing an n-doped epitaxial layer on the substrate and in the second region of the substrate;
epitaxially growing a p+-doped epitaxial layer on the n-doped epitaxial layer and in the second region of the substrate; and
removing the first mask from the second region of the substrate.

10. The method of claim 1 , wherein the first and second bismuth-containing semiconductor materials comprise doped bismuth (Bi).

11. A method comprising:
forming an isolation region in a substrate, wherein the isolation region extends to an upper surface of the substrate;
forming a first highly doped source/drain contact region adjacent a first sidewall of the isolation region;
forming a first dielectric layer over the first highly doped source/drain contact region;
forming a conductive layer over the first dielectric layer;
forming a second dielectric layer over the conductive layer;
forming a first opening through the second dielectric layer, the conductive layer, and the first dielectric layer to the first highly doped source/drain contact region; and
forming a semiconductor material in the first opening, wherein forming the semiconductor material comprises forming a bismuth-containing material in an amorphous or polycrystalline state, and further comprising annealing, the annealing crystallizing the bismuth-containing material.

12. The method of claim 11 , wherein the semiconductor material extends over an upper surface of the second dielectric layer.

13. The method of claim 11 , further comprising forming a third dielectric layer over the semiconductor material, wherein the annealing is performed after forming the third dielectric layer.

14. The method of claim 11 , wherein forming the first highly doped source/drain contact region comprises epitaxially growing a semiconductor material over the substrate.

15. The method of claim 11 , wherein the forming the first highly doped source/drain contact region comprises:
implanting a first dopant in the first region of the substrate to form a first doped well; and
implanting a second dopant in the first doped well to form a first doped region.

16. The method of claim 15 , wherein the first dopant is a p-type dopant and wherein the second dopant is an n-type dopant.

17. A method comprising:
forming a first highly doped source/drain contact region in a substrate;
forming a first dielectric layer over the first highly doped source/drain contact region;
forming a conductive layer over the first dielectric layer;
forming a second dielectric layer over the conductive layer;
forming a first opening through the second dielectric layer, the conductive layer, and the first dielectric layer to the first highly doped source/drain contact region;
forming a gate dielectric along sidewalls of the first opening;
forming a semiconductor material in the first opening, the semiconductor material having a channel region and a second highly doped so

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Colinge Jean-Pierre
• Diaz Carlos H
• Yeo Yee-Chia

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P30/22

  using masks · CPC title

• H10P14/3802

  Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth · CPC title

• H10P14/3458

  Monocrystalline · CPC title