Memory cells including vertical nanowire transistors

Patent metadata

Field	Value
Publication number	US-10312229-B2
Application number	US-201715789870-A
Country	US
Kind code	B2
Filing date	Oct 20, 2017
Priority date	Oct 28, 2016
Publication date	Jun 4, 2019
Grant date	Jun 4, 2019

Abstract

A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

First claim

What is claimed is:

1. A circuit, comprising:
an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor.

2. The circuit of claim 1 , wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.

3. The circuit of claim 2 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram.

4. The circuit of claim 2 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle.

5. The circuit of claim 2 , wherein the SRAM cell includes:
a first intra-cell connector (Q R ) connecting a current path terminal of the p-type vertical nanowire transistor (PU R ) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PD R ) in a first level and the n-type vertical nanowire transistor (PG R ) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PD L ) in first level of the first column and of the p-type vertical nanowire transistor (PU L ) in the third column; and
a second intra-cell connector (Q L ) connecting a current path terminal of the p-type vertical nanowire transistor (PU L ) in the third column to a current path terminal between the n-type vertical nanowire transistor (PD L ) in the first level and the n-type vertical nanowire transistor (PG L ) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PD R ) in first level of the second column and of the p-type vertical nanowire transistor (PU R ) in the fourth column.

6. The circuit of claim 5 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed on opposing sides of the parallelogram.

7. The circuit of claim 5 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first and second vias being disposed outside of the parallelogram.

8. The circuit of claim 5 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram, and the first intra-cell connector and the second intra-cell connector include respective first and second vias connecting the corresponding gates to the corresponding current path terminal, the first via being disposed inside of the parallelogram and the second via being disposed outside of the parallelogram.

9. The circuit of claim 1 , wherein the SRAM cell includes a first conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a first subset of the vertical nanowire transistor columns, and a second conductor disposed beneath and contacting current path terminals of vertical nanowire transistors in a second subset of the vertical nanowire transistor columns.

10. The circuit of claim 2 , wherein the SRAM cell includes a first conductor (V SS ) disposed beneath and contacting current path terminals of n-type vertical nanowire transistors in the first and second vertical nanowire transistor columns, and a second conductor (V DD ) disposed beneath and contacting current path terminals of p-type vertical nanowire transistors in the third and fourth vertical nanowire transistor columns.

11. The circuit of claim 2 , where the SRAM cell includes:
a first bit line conductor (BL) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the first vertical nanowire transistor column;
a second bit line conductor (BL/) disposed above and contacting a current path terminal of the n-type vertical nanowire transistor in the second level of the second vertical nanowire transistor column; and
a word line conductor (WL) connected to the gates of the n-type vertical nanowire transistors in the second level of the first and second vertical nanowire transistor columns.

12. A computer system adapted to process a computer implemented representation of a circuit design, comprising:
a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions to select cells from a cell library and/or to compile a memory layout using a selected cell;
the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language; and
at least one entry in the cell library, or the selected cell, comprising a specification of physical structures and timing parameters of an SRAM cell, the SRAM cell comprising a set of vertical nanowire transistor columns, each member of the set including a vertical nanowire transistor, and at least one member of the set being a vertical nanowire transistor column including a first vertical nanowire transistor on top of and connected in series to a second vertical nanowire transistor.

13. The computer system of claim 12 , wherein the set consists of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor.

14. The computer system of claim 13 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a parallelogram.

15. The computer system of claim 13 , wherein the four vertical nanowire transistor columns are arranged in layout at corners of a rectangle.

16. The computer system of claim 13 , wherein the SRAM cell includes
a first intra-cell connector (Q R ) connecting a current path terminal of the p-type vertical nanowire transistor (PU R ) in the fourth column to a current path terminal between the n-type vertical nanowire transistor (PD R ) in a first level and the n-type vertical nanowire transistor (PG R ) in a second level of the second column, and to gates of the n-type vertical nanowire transistor (PD L ) in first level of the first column and of the p-type vertical nanowire transistor (PU L ) in the third column; and
a second intra-cell connector (Q L ) connecting a current path terminal of the p-type vertical nanowire transistor (PU L ) in the third column to a current path terminal between the n-type vertical nanowire transistor (PD L ) in the first level and the n-type vertical nanowire transistor (PG L ) in the second level of the first column, and to gates of the n-type vertical nanowire transistor (PD R ) in the first level of the second column and of the p-type vertical nanowire transistor (PU R ) in the fourth column.

Assignees

• Synopsys Inc

Inventors

• Moroz Victor
• Kawa Jamil
• Nguyen Thu

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic

• H01L27/1108

  Electricity · mapped topic