Packaged electronic devices having dielectric substrates with thermally conductive adhesive layers

Patent metadata

Field	Value
Publication number	US-12224233-B2
Application number	US-202117159925-A
Country	US
Kind code	B2
Filing date	Jan 27, 2021
Priority date	Jan 27, 2021
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.

First claim

That which is claimed is:

1. A packaged electronic device, comprising:
a power semiconductor die that comprises a first terminal and a second terminal;
a lead frame comprising a lower side and an upper side that comprises a die pad region;
a first lead and a second lead;
a dielectric substrate;
a lower metal cladding layer on a lower side of the dielectric substrate;
a first metal braze layer on an upper side of the dielectric substrate; and
a second metal braze layer is between an upper side of the lower metal cladding layer and the lower side of the dielectric substrate,
wherein the power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the first metal braze layer, and
wherein the first metal braze layer is directly attached to the dielectric substrate and to the lower side of the lead frame.

2. The packaged electronic device of claim 1 , further comprising an overmold package that encapsulates an upper side and side surfaces of the power semiconductor die.

3. The packaged electronic device of claim 1 , wherein the lead frame comprises a first type of metal and the lower metal cladding layer also comprises the first type of metal.

4. The packaged electronic device of claim 1 , wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame.

5. The packaged electronic device of claim 4 , wherein the second lead is separate from the lead frame and is directly bonded to the second terminal of the power semiconductor die.

6. A packaged electronic device, comprising:
a dielectric substrate;
a first metal cladding layer on a lower side of the dielectric substrate;
a lead frame that has an upper side that comprises a die pad region and a lower side that is on an upper side of the dielectric substrate;
a first power semiconductor die that is on the die pad region of the lead frame;
a first metal braze layer between the first metal cladding layer and the dielectric substrate; and
a second metal braze layer on the upper side of the dielectric substrate, wherein the second metal braze layer is directly attached to both the upper side of the dielectric substrate and to the lower side of the lead frame.

7. The packaged electronic device of claim 6 , further comprising an overmold encapsulation that encapsulates an upper side and side surfaces of the first power semiconductor die and at least an upper side of the dielectric substrate.

8. The packaged electronic device of claim 7 , wherein the dielectric substrate comprises a ceramic substrate.

9. The packaged electronic device of claim 6 , wherein the lead frame further comprises a first lead that is integral with and electrically connected to the die pad region, the packaged electronic device further comprising a second lead that is directly bonded to a first terminal of the first power semiconductor die.

10. The packaged electronic device of claim 6 , further comprising a second power semiconductor die that is on the lead frame and electrically connected to the first power semiconductor die.

11. The packaged electronic device of claim 10 , wherein the first and second power semiconductor die are electrically connected in parallel.

12. The packaged electronic device of claim 10 , wherein a second terminal of the first power semiconductor die is electrically connected to the first lead through the lead frame, and a first terminal of the second power semiconductor die is also electrically connected to the first lead through the lead frame.

13. A packaged electronic device, comprising:
a dielectric substrate;
a first metal braze layer on an upper surface of the dielectric substrate;
a thermally-conductive adhesive paste;
a lead frame on the first metal braze layer;
a first metal cladding layer on a lower side of the dielectric substrate;
a second metal braze layer between the first metal cladding layer and the dielectric substrate;
a power semiconductor die that is mounted on an upper side of the lead frame;
an overmold encapsulation that surrounds an upper side and side surfaces of the power semiconductor die and at least partially surrounds sidewalls of the dielectric substrate while exposing at least a portion of the first metal cladding layer; and
a first lead and a second lead that each extend through the overmold encapsulation and that are electrically connected to the power semiconductor die,
wherein the power semiconductor die is electrically isolated from the first metal cladding layer, and
wherein the first metal braze layer is directly attached to the dielectric substrate and to a second metal cladding layer.

14. The packaged electronic device of claim 13 , wherein the dielectric substrate comprises a ceramic substrate.

15. The packaged electronic device of claim 13 , wherein the first lead is integral with the lead frame and is electrically connected to a first terminal of the power semiconductor die.

16. The packaged electronic device of claim 15 , wherein the second lead is directly bonded to a second terminal of the power semiconductor die.

17. The packaged electronic device of claim 13 , wherein a thermally-conductive adhesive paste is between the first metal braze layer and the lead frame.

Assignees

• Wolfspeed Inc

Inventors

• Seal Sayan
• Saxena Kuldeep
• Balaraman Devarajan

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title