Storage device and electronic device including the same

Patent metadata

Field	Value
Publication number	US-12223181-B2
Application number	US-202318197456-A
Country	US
Kind code	B2
Filing date	May 15, 2023
Priority date	Sep 14, 2022
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

A storage device includes at least one nonvolatile memory device and a storage controller. The storage controller controls the at least one nonvolatile memory device based on a request from an external host. The storage controller adaptively adjusts an impedance of a transmission driver based on a change of an operating temperature of the storage device. The transmission driver transmits a transmission signal to the external host through a link. The storage device may increase an eye height of the transmission signal transmitted to the host through the link by decreasing impedance of the transmission driver as the operating temperature increases. Therefore, the storage device according to example embodiments may maintain reliability of the link even though the operating temperature of the storage device increases.

First claim

What is claimed is:

1. A storage device comprising:
at least one nonvolatile memory device; and
a storage controller, comprising a transmission driver, configured to control the at least one nonvolatile memory device based on a request from an external host,
wherein the storage controller is configured to adaptively adjust an impedance of the transmission driver based on a change of an operating temperature of the storage device,
wherein the transmission driver is configured to transmit a transmission signal to the external host through a link, and
wherein the storage controller is further configured to decrease the impedance of the transmission driver in response to an increase of the operating temperature such that an eye height of the transmission signal is increased.

2. The storage device of claim 1 , wherein the storage controller is configured to:
transmit the transmission signal to the external host based on the impedance having a first impedance value, in response to the operating temperature being equal to or smaller than a first threshold value; and
transmit the transmission signal to the external host based on the impedance having a second impedance value smaller than the first impedance value, in response to the operating temperature exceeding the first threshold value.

3. The storage device of claim 2 , wherein the storage controller is configured to transmit the transmission signal to the external host based on the impedance having a third impedance value smaller than the second impedance value, in response to the operating temperature exceeding a second threshold value greater than the first threshold value.

4. The storage device of claim 1 , wherein the storage controller comprises:
a temperature sensor configured to sense the operating temperature of the storage device and generate an temperature signal corresponding to the operating temperature;
a temperature monitor configured to monitor the operating temperature of the storage device based on the temperature signal and generate an alert signal in response to the operating temperature exceeding at least one threshold value;
a transmission impedance controller configured to generate an impedance control code for adjusting the impedance based on the alert signal; and
a host interface circuit comprising the transmission driver configured to adjust the impedance in response to the impedance control code to adjust the eye height of the transmission signal.

5. The storage device of claim 4 , wherein the temperature monitor is configured to:
set a plurality of bits of the alert signal to have a first state in response to the operating temperature being equal to or smaller than a first threshold value of the at least one threshold value;
set the plurality of bits of the alert signal to have a second state different from the first state in response to the operating temperature exceeding the first threshold value; and
set the plurality of bits of the alert signal to have a third state different from the second state and the first state in response to the operating temperature exceeding a second threshold value greater than the first threshold value of the at least one threshold value.

6. The storage device of claim 5 , wherein the transmission impedance controller is configured to:
generate the impedance control code to have a first impedance value in response to the alert signal having the first state;
generate the impedance control code to have a second impedance value smaller than the first impedance value in response to the alert signal having the second state; and
generate the impedance control code to have a third impedance value smaller than the second impedance value in response to the alert signal having the third state.

7. The storage device of claim 6 , wherein the transmission impedance controller is configured to store a table, and
wherein the table is configured to store the first state, the second state and the third state of the alert signal, and values of the impedance control code corresponding to the first state, the second state and the third state.

8. The storage device of claim 6 , wherein the transmission impedance controller is configured to store a firmware, and
wherein the firmware is configured to store the first state, the second state and the third state of the alert signal, and values of the impedance control code corresponding to the first state, the second state and the third state.

9. The storage device of claim 6 , wherein the first impedance value is determined based on a transmission preset value and a coefficient value optimized for a third phase of equalization process of a peripheral component interconnect express (PCIe) link training between the external host and the storage controller.

10. The storage device of claim 4 , wherein the transmission driver comprises a plurality of driver segments connected in parallel between a power supply voltage and a ground voltage,
wherein the plurality of driver segments configured to receive a first sub equalized signal and a second sub equalized signal commonly from a transmission equalizer in the host interface circuit, and
wherein the transmission driver is configured to adjust the impedance by adjusting a number of driver segments, which are enabled, from among the plurality of driver segments, in response to the impedance control code.

11. The storage device of claim 10 , wherein the transmission driver is configured to increase the number of driver segments which are enabled based on an increase of the operating temperature.

12. The storage device of claim 10 , wherein each of the plurality of driver segments comprises:
a p-channel metal-oxide semiconductor (PMOS) transistor connected between the power supply voltage and a first node and having a first gate to receive a first bit of a pull-up control code of the impedance control code;
a first n-channel metal-oxide semiconductor (NMOS) transistor connected between the first node and a second node and having a second gate to receive the first sub equalized signal;
a second NMOS transistor connected between the first node and a third node in parallel with the first NMOS transistor and having a third gate to receive the second sub equalized signal;
a third NMOS transistor connected between the second node and a fourth node and having a fourth gate to receive the second sub equalized signal;
a fourth NMOS transistor connected between the third node and the fourth node in parallel with the third NMOS transistor and having a fifth gate to receive the first sub equalized signal; and
a fifth NMOS transistor connected between the fourth node and the ground voltage and having a sixth gate to receive a second bit of a pull-down control code of the impedance control code, and
wherein a first component of the transmission signal is provided at the second node and a second component of the transmission signal is provided at the third node.

13. The storage device of claim 1 , wherein the storage controller is configured to communicate with the external host based on a peripheral component interconnect express (PCIe).

14. An electronic device comprising:
a power supply configured to supply a first power and a second power;
a first solid state drive (SSD) backplane and a second SSD backplane configured to receive the first power from the power supply, the first SSD backplane comprising a first plurality of SSDs and the second SSD backplane comprising a second plurality of SSDs; and
a baseboard configured to receive the second power from the power supply, to independently power on and power off the first SSD backplane and the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jaehwan
• Ahn Yeongyu
• Yoo Hyunjung
• Lee Jungwoo

Classifications

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2213/0026

  PCI express · CPC title