Calibrating I/O impedances using estimation of memory die temperature

Patent metadata

Field	Value
Publication number	US-10062453-B1
Application number	US-201715454665-A
Country	US
Kind code	B1
Filing date	Mar 9, 2017
Priority date	Mar 9, 2017
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

A memory system includes a calibration engine, a memory, and a memory controller coupled to the memory by a channel used to transmit a plurality of commands from the memory controller to the memory. The memory controller estimates a total energy consumed based on the first plurality of commands in a first sampling period and determines a first temperature change of the memory based on the first total energy consumed. The memory controller transmits an impedance calibration command to the calibration engine if the first temperature change of the memory exceeds a first threshold. The calibration engine changes an impedance of an I/O terminal of the memory based on the calibration command.

First claim

What is claimed is:

1. A memory system comprising:
a memory having an input/output (“I/O”) terminal, the I/O terminal having an associated termination impedance;
a calibration engine configured to change the termination impedance of the I/O terminal based on an impedance calibration command;
a memory controller communicatively coupled by a channel to the I/O terminal and configured to transmit a first plurality of commands over the channel to the memory, the memory controller further configured to:
estimate a first total energy consumed based on the first plurality of commands during a first sampling period;
determine a first temperature change of the memory based on the first total energy consumed in the first sampling period and a previous total energy consumed in a previous sampling period; and
transmit the impedance calibration command to the calibration engine if the first temperature change of the memory exceeds a first threshold.

2. The memory system of claim 1 , wherein the memory controller is further configured to store the first temperature change as a new threshold.

3. The memory system of claim 1 , wherein if the first temperature change does not exceed the first threshold, the memory controller is configured to:
estimate a second temperature change of the memory based on a second plurality of commands during a second sampling period compared to the previous total energy consumed in the previous sampling period; and
transmit the impedance calibration command to the calibration engine if the second temperature change exceeds the first threshold.

4. The memory system of claim 1 , wherein the first total energy consumed is calculated from a tally of the first plurality of commands, an average current for each of the plurality of commands, and a time for each of the first plurality of commands.

5. The memory system of claim 4 , wherein the memory controller includes a stored table of the average or peak current for each of the plurality of commands.

6. The memory system of claim 5 , wherein the average or peak current for a particular command of the plurality of commands is programmable.

7. The memory system of claim 6 , wherein the estimation of the first total energy consumed includes a heat dissipation component.

8. The memory system of claim 1 , wherein the first total energy consumed is estimated from a weighted average temperature change associated with each command of the first plurality of commands.

9. The memory system of claim 1 , wherein the memory controller transmits the impedance calibration command over a sideband channel and via a special command on the sideband channel.

10. The memory system of claim 1 , wherein the impedance calibration command is a short calibration command (ZQCS).

11. The memory system of claim 1 , wherein a long calibration command (ZQCL) is transmitted to the calibration engine if the first temperature change exceeds the first threshold and a second threshold.

12. The memory system of claim 1 , wherein the calibration engine is configured to execute a periodic background calibration of the I/O terminal.

13. The memory system of claim 1 , wherein the calibration engine is configured to change the impedance of the I/O terminal on a controller-side of the channel.

14. The memory system of claim 1 , wherein the calibration engine is configured to change the impedance of the I/O terminal on a memory-side of the channel.

15. A method of calibrating I/O impedances using an estimation of temperature, the method comprising:
recording, at a memory controller, a tally of commands transmitted to a memory within a sampling period;
receiving a signal that the sampling period is complete;
determining, at the memory controller, a total energy consumed associated with the transmitted commands in the tally;
determining a temperature change based on the total energy consumed compared to a previous total energy consumed in a previous sampling period;
transmitting a calibration command to a calibration engine if the temperature change exceeds at least one threshold value.

16. The method of claim 15 , wherein determining the total energy consumed comprises integrating an average or peak current for each of the transmitted commands in the tally and a time period for each of the commands.

17. The method of claim 16 , wherein determining the total energy consumed further comprises subtracting a heat dissipation component.

18. The method of claim 15 , wherein transmitting the calibration command to the calibration engine includes transmitting the calibration command over a sideband channel and via a special command on the sideband channel.

19. The method of claim 15 , wherein transmitting the calibration command to the calibration engine includes transmitting a short calibration command (ZQCS) if the temperature change exceeds a first threshold but does not exceed a second threshold.

20. The method of claim 15 , further comprising transmitting a long calibration command (ZQCL) to the calibration engine if a temperature difference exceeds a first threshold and a second threshold.

Assignees

• Toshiba Memory Corp

Inventors

• Griffin Jason

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/46

  Test trigger logic · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/022

  in I/O circuitry · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title