Memory device with dynamic cache management

Patent metadata

Field	Value
Publication number	US-10509722-B2
Application number	US-201715693178-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Aug 31, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.

First claim

We claim:

1. A memory system, comprising:
a memory array including a plurality of memory cells; and
a controller coupled to the memory array, the controller configured to:
select a garbage collection (GC) source block storing valid data,
calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and
designate a storage mode for an available memory block based on the valid data measure, wherein:
memory cells of the available memory block are configured to store up to N bits and are in an erased state, and
the storage mode is for configuring the memory cells as cache memory that store M bits for subsequent or upcoming data writes, wherein M<N.

2. The memory system of claim 1 wherein the controller is further configured to designate single-level cell (SLC) mode for the storage mode based on comparing the valid data measure to a decision threshold.

3. The memory system of claim 2 wherein the controller is configured to designate the SLC mode based on the decision threshold representing a threshold amount of the valid data stored in the GC source block, wherein the threshold amount is configurable and is greater than zero and less than 25% of a total capacity of the GC source block.

4. The memory system of claim 3 wherein the threshold amount is 10% of a total capacity of the GC source block.

5. The memory system of claim 1 wherein the controller is further configured to designate the storage mode for the available memory block that is indicated by a host cursor for the subsequent or upcoming data writes.

6. The memory system of claim 1 wherein the controller is further configured to designate the storage mode for the available memory block that is indicated by a GC cursor for the subsequent or upcoming data writes.

7. The memory system of claim 1 wherein the controller is further configured to:
determine a low logic saturation state for the memory array; and
designate a SLC mode for the storage mode based on the low logic saturation state.

8. The memory system of claim 1 wherein the controller is configured to designate the storage mode as a SLC mode under steady-state.

9. The memory system of claim 8 wherein:
the memory array includes static SLC blocks designated as static cache, wherein the static SLC blocks store one bit per cell; and
the controller is further configured to designate the storage mode for a dynamic SLC caching function for utilizing extra-level cell (XLC) units, capable of holding multiple bits of the data, to operate in the SLC mode and store one bit per cell as the cache memory in addition to the static cache.

10. The memory system of claim 1 wherein the controller is configured to designate a XLC mode for the storage mode when the valid data measure is not less than a decision threshold.

11. The memory system of claim 1 wherein the controller is configured to select the GC source block including a grouping of the memory cells operating in SLC mode.

12. The memory system of claim 1 wherein the memory cells are non-volatile.

13. The memory system of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of an amount of the data previously written in the SLC mode.

14. The memory system of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of a data desirability measure associated with a performance model for characterizing the previously stored data.

15. A method of operating a memory system including a controller and memory array including memory cells, the method comprising:
selecting a GC source block storing valid data;
calculating a valid data measure for the GC source block for representing an amount of the valid data within the GC source block; and
designating a storage mode for an available memory block based on the valid data measure, wherein:
memory cells of the available memory block are configured to store up to N bits are in an erased state, and
the storage mode is for configuring the memory cells as cache memory that store M bits for subsequent or upcoming data writes, wherein M<N.

16. The method of claim 15 , wherein designating the storage mode includes designating the storage mode for the available memory block that is indicated by a host cursor for the subsequent or upcoming data writes.

17. The method of claim 15 , wherein designating the storage mode includes designating the storage mode for the available memory block that is indicated by a GC cursor for the subsequent or upcoming data writes.

18. The method of claim 15 , wherein designating the storage mode includes designating a XLC mode for the storage mode when the valid data measure is not less than a decision threshold.

19. The method of claim 15 , wherein designating the storage mode includes designating a SLC mode for the storage mode when the valid data measure is less than a decision threshold.

20. The method of claim 19 , wherein designating the SLC mode includes designating the SLC mode regardless of an amount of the data previously written in the SLC mode, regardless of a data desirability measure associated with a performance model for characterizing the previously stored data, or a combination thereof.

21. The method of claim 19 , wherein designating the SLC mode includes designating the SLC mode based on the decision threshold representing a threshold amount of the valid data stored in the GC source block, wherein the threshold amount is configurable and is greater than zero and less than 25% of a total capacity of the GC source block.

22. The method of claim 21 , wherein designating the SLC mode includes configuring the threshold amount to 10% of a total capacity of the GC source block.

23. A method of operating a memory system including a controller and memory array including memory cells, the method comprising:
writing data in the memory cells under steady-state;
selecting a GC source block for representing a grouping of the memory cells,
wherein the GC source block is a target of a GC function configured to copy valid data to another set of memory cells and erase information stored in GC source block in availing the GC source block for subsequent or upcoming data writes;

calculating a valid data measure for the GC source block for representing an amount of the valid data stored within the GC source block; and
designating a SLC mode for an available memory block when the valid data measure is less than a decision threshold, wherein:
memory cells of the available memory block are XLC units and are in an erased state, and
the SLC mode is for operating the XLC units capable of holding multiple bits to store one bit per cell as cache memory for the subsequent or upcoming data writes.

24. The method of claim 23 , wherein designating the SLC mode includes designating the SLC mode for the available memory block that is indicated by a host cursor or a GC cursor.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Feeley Peter
• Malshe Ashutosh
• Hubbard Daniel J
• Hale Christopher S
• Brandt Kevin R
• Ratnam Sampath K
• Li Yun
• Hamilton Marc S

Classifications

• G06F12/0253 Primary

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G06F2212/2022

  Flash memory · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title

• G11C11/5621

  using charge storage in a floating gate · CPC title