Memory device with dynamic cache management

Patent metadata

Field	Value
Publication number	US-11593261-B2
Application number	US-202117374906-A
Country	US
Kind code	B2
Filing date	Jul 13, 2021
Priority date	Aug 31, 2017
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

First claim

We claim:

1. A memory system, comprising:
a memory array including a plurality of memory cells; and
a controller coupled to the memory array, the controller configured to:
designate a storage mode for a target set of memory cells based on valid data stored in a source block, wherein
the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and
the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

2. The memory system of claim 1 , wherein the source block is associated with a garbage collection (GC) process.

3. The memory system of claim 2 , wherein the controller is configured to designate single-level cell (SLC) mode for the storage mode when the valid data associated with the GC process is below a decision threshold.

4. The memory system of claim 2 wherein the controller is configured to designate an extra-level cell (XLC) mode for the storage mode when the valid data is not less than a decision threshold.

5. The memory system of claim 2 , wherein:
the source block is a GC source block; and
the controller is further configured to:
calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block; and
designate the target set of memory cells to operate in SLC mode based on comparing the valid data measure to a decision threshold.

6. The memory system of claim 1 , wherein the decision threshold corresponds to operating the target set of memory cells in the SLC mode when the valid data within the source block is less than 25% of a total capacity of the source block.

7. The memory system of claim 1 wherein the target set of memory cells is indicated by a host cursor for the subsequent or upcoming data writes.

8. The memory system of claim 1 wherein the target set of memory cells is indicated by a GC cursor for the subsequent or upcoming data writes.

9. The memory system of claim 1 wherein the controller is further configured to:
determine a low logic saturation state for the memory array; and
designate SLC mode for the storage mode based on the low logic saturation state.

10. The memory system of claim 1 wherein the controller is configured to designate the storage mode as SLC mode under steady-state.

11. The memory system of claim 1 wherein the memory array includes static SLC blocks designated as static cache, wherein the static SLC blocks store one bit per cell and is separate from the target set of memory cells.

12. The memory system of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of an amount of the data previously written in the SLC mode.

13. The memory system of claim 1 wherein the controller is configured to designate the storage mode as SLC mode for the subsequent or upcoming data writes regardless of a data desirability measure associated with a performance model for characterizing the previously stored data.

14. A method of operating a memory system including a controller and memory array including memory cells, the method comprising:
selecting a source block storing valid data; and
designating a storage mode for a target set of memory cells based on the valid data,
wherein the storage mode is for dynamically configuring the target set of memory cells as cache memory that stores a number of bits per cell less than the corresponding maximum storage capacity.

15. The method of claim 14 , wherein the source block is selected for a GC process.

16. The method of claim 14 , wherein the target set of memory cells is indicated by a host cursor for a subsequent or upcoming data writes.

17. The method of claim 14 , wherein the target set of memory cells is indicated by a GC cursor for a subsequent or upcoming data writes.

18. The method of claim 14 , wherein designating the storage mode includes designating a SLC mode for the storage mode when the valid data is less than a decision threshold.

19. The method of claim 18 , wherein designating the SLC mode includes designating the SLC mode regardless of an amount of the data previously written in the SLC mode, regardless of a data desirability measure associated with a performance model for characterizing the previously stored data, or a combination thereof.

20. The method of claim 14 , wherein designating the storage mode includes designating the storage mode as SLC mode under steady-state.

Assignees

• Micron Technology Inc

Inventors

• Muchherla Kishore Kumar
• Feeley Peter
• Malshe Ashutosh
• Hubbard Daniel J
• Hale Christopher S
• Brandt Kevin R
• Ratnam Sampath K
• Li Yun
• Hamilton Marc S

Classifications

• G06F2212/702

  Conservative garbage collection · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title

• G06F12/0646

  Configuration or reconfiguration · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0893 Primary

  Caches characterised by their organisation or structure · CPC title