Data latch programming algorithm for multi-bit-per-cell memory devices

Patent metadata

Field	Value
Publication number	US-2023402113-A1
Application number	US-202217838717-A
Country	US
Kind code	A1
Filing date	Jun 13, 2022
Priority date	Jun 13, 2022
Publication date	Dec 14, 2023
Grant date	—

Abstract

A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to receive and store program page data and utilizing a second data latch to store bit information indicating which cells are to be targeted for the multi-stage programming. At each program stage, a respective program loop may be performed with respect to each threshold voltage distribution generated during a prior program stage to create two new threshold voltage distributions from the prior distribution.

First claim

What is claimed is:

1 . A method of multi-stage programming of a multi-bit-per-cell memory array, the method comprising:
receiving first program data corresponding to a first page level into a first data latch; performing an initial program stage of the multi-stage programming to generate a plurality of threshold voltage distributions based on the first program data corresponding to the first page level; and performing one or more additional program stages, wherein performing each additional program stage comprises performing a program loop for each threshold voltage distribution generated during a prior program stage, the performing the program loop comprising splitting the threshold voltage distribution generated during the prior program stage into two new threshold voltage distributions.

2 . The method of claim 1 , wherein performing a particular program loop of a current additional program stage for an addressed prior threshold voltage distribution generated during the prior program stage comprises:
determining, based on data stored in a second data latch, a set of memory cells of the multi-bit-per-cell memory array that is in the addressed prior threshold voltage distribution; and programming the set of memory cells to shift their threshold voltages to states corresponding to program data currently stored in the first data latch.

3 . The method of claim 2 , wherein programming the set of memory cells causes the addressed prior threshold voltage distribution to be split into two new threshold voltage distributions associated with the current additional program stage.

4 . The method of claim 3 , wherein each of the two new threshold voltage distributions generated from the addressed prior threshold voltage distribution is shifted towards a higher threshold voltage than the particular prior threshold voltage distribution.

5 . The method of claim 2 , wherein determining, based on the data stored in the second data latch, the set of memory cells that is in the addressed prior threshold voltage distribution comprises determining that bit information stored in the second data latch for each memory cell in the set of memory cells comprises a first bit value indicating that the cell has a threshold voltage that falls within the addressed prior threshold voltage distribution.

6 . The method of claim 5 , wherein determining the set of memory cells further comprises excluding from the set of memory cells each memory cell associated with bit information in the second data latch comprising a second bit value different from the first bit value.

7 . The method of claim 5 , wherein performing the current additional program stage further comprises updating the data stored in the second data latch based on the memory cell programming performed during the particular program loop.

8 . The method of claim 5 , wherein updating the data stored in the second data latch comprises updating the bit information corresponding to the set of memory cells to flip each first bit value to a second bit value indicating at least one of: i) that a corresponding cell in the set of memory cells was successfully programmed or ii) that the corresponding cell is not within a next addressed prior threshold voltage distribution associated a next program loop of the current additional program stage.

9 . The method of claim 2 , wherein the data stored in the second data latch is internal data load (IDL) information.

10 . The method of claim 1 , wherein performing each additional program stage comprises generating a number of new threshold voltage distributions that is twice a number of threshold voltage distributions generated during the prior program stage.

11 . A controller for a memory device, the controller configured to execute instructions to perform a multi-stage programming process for a multi-bit-per-cell memory array of the memory device, the multi-stage programming process comprising:
performing a current program stage based at least in part on program data stored in a first data latch, wherein performing the current program stage comprises programming a set of memory cells identified based on data stored in a second data latch to generate a plurality of new threshold voltage distributions from each threshold voltage distribution generated during a prior program stage; and performing one or more additional program stages based at least in part on a number of bits stored in each memory cell multi-bit-per-cell memory array.

12 . The controller of claim 11 , wherein the controller is configured to perform a total number of program stages equal to the number of bits stored in each memory cell.

13 . The controller of claim 12 , wherein the controller is configured to perform the multi-stage programming process using only the first data latch and the second data latch among a set of data latches contained in sense amplifier data latch (SADL) peripheral circuitry.

14 . The controller of claim 11 , wherein the controller is configured to utilize a third data latch to reduce a total number of program stages needed to program the multi-bit-per-cell memory array to less than the number of bits stored in each memory cell.

15 . The controller of claim 14 , wherein use of the third data latch reduces the total number of program stages by half.

16 . The controller of claim 14 , wherein the first data latch stores first program data corresponding to a first page level and the third data latch stores second program data corresponding to a second page level immediately above the first page level in page level hierarchy.

17 . The controller of claim 14 , wherein the second data latch stores first internal data load (IDL) bit information and the third data latch stores second IDL bit information.

18 . The controller of claim 14 , wherein the third data latch enables one of: i) generating four new threshold voltage distributions from each threshold voltage distribution generated during the prior program stage or ii) concurrently generating a respective two new threshold voltage distributions from each of two threshold voltage distributions generated during the prior program stage.

19 . A circuit, comprising:
a first data latch configured to receive program data at a corresponding page level; and a second data latch configured to store bit information indicative of which memory cells of a multi-bit-per-cell memory array to program as part of a multi-stage programming process, wherein the multi-stage programming process comprises multiple program stages, and wherein, during a particular program stage, a series of program loops are performed, each program loop comprising identifying a set of memory cells in the multi-bit-per-cell memory array that are within a selected threshold voltage distribution generated during a prior program stage and programming the set of memory cells based on the program data stored in the first data latch to divide the selected threshold voltage distribution into a plurality of new threshold voltage distributions.

20 . The circuit of claim 19 , wherein the multi-stage programming process is performed using only the first data latch and the second data latch among a plurality of data latches contained in the circuit.

Assignees

• Sandisk Technologies Llc

Inventors

• Miwa Toru
• Toyama Fumiaki

Classifications

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C7/1039

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title