Semiconductor device with channel pattern formed of stacked semiconductor regions and gate electrode parts

Patent metadata

Field	Value
Publication number	US-12211941-B2
Application number	US-202117327725-A
Country	US
Kind code	B2
Filing date	May 23, 2021
Priority date	Dec 1, 2020
Publication date	Jan 28, 2025
Grant date	Jan 28, 2025

Abstract

A semiconductor device includes; an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack, and a gate electrode extending across the channel pattern. The semiconductor patterns includes a first semiconductor pattern and a second semiconductor pattern. The gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern. A width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having an active pattern;
a source/drain pattern on the active pattern of the substrate, the source/drain pattern extending to a depth below an uppermost surface of the active pattern of the substrate;
a channel pattern connected to the source/drain pattern and including semiconductor patterns spaced apart in a vertical stack over the uppermost surface of the active pattern of the substrate; and
a gate electrode extending across the channel pattern,
wherein the semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern over the first semiconductor pattern,
the gate electrode includes a first part between the substrate and the first semiconductor pattern and a second part between the first semiconductor pattern and the second semiconductor pattern,
a first gate insulating layer is interposed between a lower surface of the first part and the uppermost surface of the active pattern of the substrate, and between an upper surface of the first part and a lower surface of the first semiconductor pattern,
a second gate insulating layer is interposed between a lower surface of the second part and an upper surface of the first semiconductor pattern, and between an upper surface of the second part and a lower surface of the second semiconductor pattern,
the first gate insulating layer physically contacts the lower surface of the first part and the uppermost surface of the active pattern of the substrate,
the source/drain pattern including a side wall, the side wall of the source/drain pattern including first protrusions that protrude outwardly from adjacent portions of the side wall in a direction towards the first part and second protrusions protrude outwardly from adjacent portions of the side wall in a direction towards the second part,
the first gate insulating layer includes a side wall physically contacting the first protrusions, the side wall of the first gate insulating layer including a first recess, and the first protrusions of the source/drain pattern protruding into the first recess,
the second gate insulating layer includes a side wall physically contacting the second protrusions, the side wall of the second gate insulating layer including a second recess, and the second protrusions of the source/drain pattern protruding into the second recess, and
a width of the first part varies with a depth of the first part, such that a width of a middle portion of the first part is less than a width of a lower portion of the first part and a width of an upper portion of the first part.

2. The semiconductor device of claim 1 , wherein the source/drain pattern is an N-type source/drain pattern and includes a bottom surface contacting the substrate at the depth below the uppermost surface of the active pattern of the substrate.

3. The semiconductor device of claim 1 , wherein the first part has recessed side walls, the recessed side walls face the first protrusions, and the recessed side walls have a profile that conforms with a profile of the first protrusions.

4. The semiconductor device of claim 1 , wherein the width of the lower portion is greater than the width of the upper portion.

5. The semiconductor device of claim 4 , wherein a minimum width of the second part is less than the width of the middle portion of the first part.

6. The semiconductor device of claim 5 , wherein the semiconductor patterns further include a third semiconductor pattern over the second semiconductor pattern,
the gate electrode further includes a third part between the second semiconductor pattern and the third semiconductor pattern, and
a minimum width of the third part is less than the minimum width of the second part.

7. The semiconductor device of claim 1 , wherein each of the first part and the second part includes:
a contact segment adjacent to the source/drain pattern and having a recessed side wall; and
an extension segment extending from the contact segment in a direction away from the recessed side wall and including a protruding pattern that protrudes in a direction perpendicular to a top surface of the substrate.

8. The semiconductor device of claim 7 , wherein a thickness of the contact segment is less than a thickness of the extension segment.

9. The semiconductor device of claim 1 , further comprising:
an active contact coupled to the source/drain pattern and including an upper dielectric pattern; and
a gate contact coupled to the gate electrode.

10. The semiconductor device of claim 1 , wherein the first gate insulating layer and the second gate insulating layer each comprise a high-k dielectric layer.

11. A semiconductor device, comprising:
a substrate having an active pattern;
an N-type source/drain pattern on the active pattern including a bottom surface contacting the substrate at a depth below an uppermost surface of the active pattern;
a channel pattern connected to the N-type source/drain pattern and including semiconductor patterns spaced apart in a vertical stack over the uppermost surface of the active pattern of the substrate, wherein the semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern;
a gate electrode extending across the channel pattern and including a first part between the substrate and the first semiconductor pattern; and
a gate insulating layer interposed between a lower surface of the first part and the uppermost surface of the active pattern of the substrate, wherein the gate insulating layer physically contacts the lower surface of the first part and the uppermost surface of the active pattern of the substrate,
wherein the N-type source/drain pattern includes a side wall, the side wall of the N-type source/drain pattern includes first protrusions, the first protrusions protrude from adjacent portions of the side wall in a direction toward the first part, the first part includes a recessed side wall, and the recessed side wall faces the first protrusions and has a profile that conforms to a profile of the first protrusions, and
the recessed side wall physically contacts the first protrusions, the recessed side wall of the gate insulating layer includes a recess, and the first protrusions of the N-type source/drain pattern protrude into the recess.

12. The semiconductor device of claim 11 , wherein the gate electrode further includes a second part between the first semiconductor pattern and the second semiconductor pattern, and
a minimum width of the first part is greater than a minimum width of the second part.

13. The semiconductor device of claim 12 , wherein each of the first part and the second part includes:
a contact segment adjacent to the N-type source/drain pattern and including a recessed side wall; and
an extension segment extending from the contact segment in a direction away from the recessed side wall, and including a protruding pattern that protrudes in a direction perpendicular to a top surface of the substrate.

14. The semiconductor device of claim 11 , wherein width of the first part varies with depth of the first part, decreasing to a minimum value and then increasing as the depth extends in a direction perpendicular to a top surface of the substrate.

15. The semiconductor device of claim 14 , wherein the first part includes a lower portion having a first width, a middle portion having a second width, and an upper portion having a third width greater than the second width and less than the first width.

16. A semiconductor device, comprising:
a substrate

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yeom Donghyuk
• Kim Junkyum
• Lee Kwan Heum
• Park Seonghwa
• Seo Sohyun

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title