Semiconductor device

Patent metadata

Field	Value
Publication number	US-2018294331-A1
Application number	US-201715823961-A
Country	US
Kind code	A1
Filing date	Nov 28, 2017
Priority date	Apr 5, 2017
Publication date	Oct 11, 2018
Grant date	—

Abstract

A semiconductor device includes: a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.

First claim

1 . A semiconductor device comprising:
a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.

2 . The semiconductor device of claim 1 , wherein the source/drain protection layer comprises a regrowth layer that is regrown on a sidewall of the at least one nano-sheet.

3 . The semiconductor device of claim 1 , wherein the source/drain protection layer is disposed in a sheet recess region that is recessed from a sidewall of an outer spacer defining the at least one nano-sheet, in the first direction.

4 . (canceled)

5 . The semiconductor device of claim 1 , wherein the source/drain protection layer is further disposed between the source/drain region and the gate in the first direction.

6 . The semiconductor device of claim 1 , wherein an inner spacer is further disposed between the source/drain region and the gate, and between the nano-sheets.

7 . The semiconductor device of claim 6 , wherein the source/drain protection layer is further disposed between the inner spacer and the gate in the first direction.

8 . The semiconductor device of claim 6 , wherein the source/drain protection layer is further disposed between the inner spacer and the nano-sheet, at a side of the inner spacer.

9 . The semiconductor device of claim 6 , wherein the inner spacer is disposed in a recess region that is recessed from a sidewall of the nano-sheets in the first direction.

10 . (canceled)

11 . The semiconductor device of claim 9 , wherein the source/drain protection layer and the inner spacer are formed as a single unit.

12 . The semiconductor device of claim 1 , wherein the gate comprises a main gate portion having a first thickness on the at least one nano-sheet in a direction perpendicular to the first direction and a plurality of sub-gate portions having a second thickness in said direction perpendicular to the first direction and disposed between the at least one nano-sheet and the fin-type active region, the second thickness being smaller than the first thickness.

13 . The semiconductor device of claim 12 , wherein a thickness of the lowermost sub-gate portion from among the plurality of sub-gate portions is greater than those of the other sub-gate portions.

14 . The semiconductor device of claim 12 , wherein a buffer semiconductor layer is disposed on two sidewalls of the sub-gate portion that is close to the fin-type active region from among the plurality of sub-gate portions.

15 . A semiconductor device comprising:
a substrate having an active region; at least one nano-sheet stack structure spaced apart from an upper surface of the active region and facing the upper surface of the active region, the at least one nano-sheet stack structure including a plurality of nano-sheets each having a channel region; a gate extending on the active region to cross the active region and covering the at least one nano-sheet stack structure, wherein the gate comprises a main gate portion on the at least one nano-sheet stack structure and a sub-gate portion disposed below each of the plurality of nano-sheets; a gate insulating layer between the at least one nano-sheet stack structure and the gate; a source/drain region on the active region on both sides of the at least one nano-sheet stack structure; an outer spacer on the plurality of nano-sheets and covering a sidewall of the main gate portion; inner spacers between the source/drain region and the gate, and between the plurality of nano-sheets; and a source/drain protection layer on a sidewall of the at least one nano-sheet stack structure and between the source/drain region and the at least one nano-sheet stack structure.

16 . (canceled)

17 . The semiconductor device of claim 15 , wherein the source/drain protection layer is disposed in a sheet recess portion that is recessed inwardly from a sidewall of the outer spacer.

18 . (canceled)

19 . The semiconductor device of claim 15 , wherein the source/drain protection layer is further disposed between the source/drain region and the gate insulating layer.

20 . The semiconductor device of claim 15 , wherein the source/drain protection layer is further disposed between the corresponding inner spacer and the gate.

21 .- 23 . (canceled)

24 . The semiconductor device of claim 15 , wherein a length of each sub-gate portion disposed below each of the plurality of nano-sheets is greater than a length of the main gate portion in a direction parallel to an upper surface of the substrate.

25 . A semiconductor device comprising:
a fin-type active region protruding from a substrate and extending in a first direction; a plurality of nano-sheets that are spaced apart from an upper surface of the fin-type active region and spaced apart from one another in parallel to the upper surface of the fin-type active region, each of the plurality of nano-sheets having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of each of the plurality of nano-sheets, wherein the gate comprises a main gate portion on at least one nano-sheet and a plurality of sub-gate portions disposed between the nano-sheets and the fin-type active region; a gate insulating layer between the nano-sheets and the gate; a source/drain region on the fin-type active region on opposite sides of the at least one nano-sheet; inner spacers between the source/drain region and the sub-gate portion and between the nano-sheets; and a source/drain protection layer on a sidewall of the at least one nano-sheet, and between the source/drain region and the at least one nano-sheet.

26 . (canceled)

27 . The semiconductor device of claim 25 , wherein the source/drain protection layer is further disposed between the source/drain region or the inner spacer and the gate.

28 . (canceled)

29 . (canceled)

30 . The semiconductor device of claim 25 , wherein the inner spacer is formed on each sidewall of the plurality of sub-gate portions, and the inner spacer is convex towards the gate in the first direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Edward Nam-Kyu
• Kwon Tae-Soon
• Lim Bo-Ra
• Lee Jeong-Yun

Classifications

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/7831

  Electricity · mapped topic

• H01L29/0669

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic