Forming nanosheet transistor using sacrificial spacer and inner spacers

Patent metadata

Field	Value
Publication number	US-10424651-B2
Application number	US-201815880757-A
Country	US
Kind code	B2
Filing date	Jan 26, 2018
Priority date	Jan 26, 2018
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

First claim

What is claimed is:

1. A method of fabricating a nanosheet transistor comprising:
receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer and at least one silicon-germanium (SiGe) layer,
wherein the substrate structure further includes a fin formed on the stacked set of nanosheet layers,
a gate region formed within the fin, and
a trench region adjacent to the fin;
forming a top sacrificial spacer upon the fin and the trench region;
etching the top sacrificial spacer and the nanosheet layers to form a trench in the trench region and remove portions of the top sacrificial layer, the top sacrificial layer remaining on at least one side of the fin;
forming an indentation within the at least one SiGe layer in the trench region;
forming a sacrificial inner spacer within the indentation;
etching the sacrificial inner spacer to substantially remove portions of the sacrificial inner spacer deposited on the at least one Si layer;
forming a source/drain (S/D) region within the trench;
etching the sacrificial top spacer and
sacrificial inner spacer to form an inner spacer cavity between the S/D region and the at least one SiGe layer;
forming a final top spacer on the fin;
and simultaneously forming an inner spacer within the inner spacer cavity.

2. The method of claim 1 , further comprising: etching the final top spacer to substantially remove the final top spacer from the S/D region.

3. The method of claim 1 , further comprising: depositing a gate material within the gate region; forming a cap upon the gate material; and forming a contact upon the S/D region.

4. The method of claim 3 , wherein the gate material is a high-K metallic gate (HKMG) material.

5. The method of claim 1 , further comprising: expanding the inner spacer cavity by an etching process.

6. The method of claim 5 , wherein expanding the inner spacer cavity includes using an isotropic wet etching process.

7. The method of claim 1 , further comprising: depositing a gate liner upon the fin.

8. The method of claim 7 , further comprising: etching the gate liner from the fin.

9. The method of claim 1 , wherein forming the top sacrificial spacer upon the fin and the trench region includes depositing the top sacrificial spacer upon the fin and the trench region.

10. The method of claim 1 , wherein etching the top sacrificial spacer to form the trench in the trench region and remove the portions of the top sacrificial layer includes a reactive-ion etching (RIE) process.

11. The method of claim 1 , wherein etching the sacrificial top spacer and sacrificial inner spacer includes a wet etching process.

12. The method of claim 1 , wherein the final top spacer is formed of a low dielectric constant (low-K) material.

13. The method of claim 1 , wherein the set of nanosheet layers are stacked upon an isolation layer, and wherein the isolation layer is disposed upon the substrate.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Frougier Julien
• Loubet Nicolas

Classifications

• H10P50/283

  by chemical means · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66742

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic