Vertical tunneling field-effect transistor cell and fabricating the same

Patent metadata

Field	Value
Publication number	US-10490654-B2
Application number	US-201816227931-A
Country	US
Kind code	B2
Filing date	Dec 20, 2018
Priority date	Jan 18, 2013
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

First claim

What is claimed is:

1. A tunneling field-effect transistor (TFET) comprising:
a protrusion that extends vertically from a substrate;
a drain region in a bottommost portion of the protrusion;
a source region in a topmost portion of the protrusion;
a gate stack that wraps a middle portion of the protrusion, wherein the gate stack further wraps around a portion of the source region and a portion of the drain region;
spacers along a portion of the topmost portion of the protrusion;
a drain contact coupled to the drain region;
a gate contact coupled to the gate stack; and
a source contact coupled to the source region, wherein the source contact has a width that is greater than a width of the source region and the source contact is disposed on the source region and a portion of the spacers.

2. The TFET of claim 1 , wherein a width of the spacers is greater than a width of a gating surface of the gate stack.

3. The TFET of claim 1 , further comprising a dielectric layer, wherein the drain contact, the gate contact, and the source contact extend through the dielectric layer respectively to the drain region, the gate stack, and the source region.

4. The TFET of claim 3 , wherein a portion of the dielectric layer is disposed between the substrate and a bottom surface of the gate stack.

5. The TFET of claim 3 , wherein a portion of the dielectric layer is disposed between a bottom surface of the spacers and a top surface of the gate stack.

6. The TFET of claim 1 , wherein the spacers include silicon, nitrogen, carbon, oxygen, or a combination thereof.

7. The TFET of claim 1 , wherein the width of the source contact is less than a sum of the width of the source region and the width of the spacers.

8. The TFET of claim 1 , wherein a dopant type of the source region is different than a dopant type of the drain region.

9. The TFET of claim 1 , wherein the protrusion has tapered sidewalls.

10. A tunneling field-effect transistor (TFET) comprising:
a frustoconical protrusion structure disposed over a substrate, wherein the frustoconical protrusion structure includes:
a drain region that includes a first drain portion surrounded by a dielectric layer and a second drain portion surrounded by a gate stack,
a source region that includes a first source portion surrounded by a dielectric spacer and a second source portion surrounded by the gate stack,
a region disposed between the drain region and the source region that is surrounded by the gate stack, wherein:
the dielectric spacer is disposed on a topmost surface of the gate stack and the dielectric layer is disposed between a bottommost surface of the gate stack and the substrate,
a width of the dielectric spacer is greater than a width of the topmost surface of the gate stack, and
a total width of the gate stack is less than a total width of the drain region and greater than a total width of the frustoconical protrusion structure.

11. The TFET of claim 10 , wherein the drain region is further disposed in the substrate adjacent to the frustoconical protrusion structure, wherein a width of the drain region in the frustoconical protrusion structure is less than a width of the drain region in the substrate.

12. The TFET of claim 10 , wherein a dopant type of the source region is different than a dopant type of the drain region.

13. The TFET of claim 10 , wherein a material of the dielectric spacer is different than a material of the dielectric layer.

14. The TFET of claim 13 , wherein the dielectric spacer includes silicon and nitrogen and the dielectric layer includes silicon and oxygen.

15. The TFET of claim 10 , wherein the gate stack includes a high-k dielectric layer and a metal gate layer.

16. The TFET of claim 10 , further comprising:
a source contact that extends through the dielectric layer to the source region;
a gate contact that extends through the dielectric layer to the gate stack; and
a drain contact that extends through the dielectric layer to the drain region.

17. The TFET of claim 16 , wherein a critical dimension of the source contact is equal to a width of the source region plus an overlay limit.

18. The TFET of claim 10 , wherein the frustoconical protrusion structure has tapered sidewalls, such that the source region and the drain region each have a tapered width.

19. A tunneling field-effect transistor (TFET) comprising:
a silicon substrate;
a silicon protrusion formed from the silicon substrate and extending up from a top surface of the silicon substrate;
a first doped region of a first type dopant in the silicon protrusion, wherein the first doped region is configured as a source region;
a second doped region of a second type dopant that extends from the silicon substrate into the silicon protrusion, wherein the second doped region is configured as a drain region, wherein the second type dopant is different than the first type dopant;
a gate stack that wraps a portion of the first doped region, a portion of the second doped region, and a portion of the silicon protrusion disposed between the first doped region and the second doped region; and
a silicon-and-nitrogen comprising spacer that wraps another portion of the first doped region, such that the silicon-and-nitrogen comprising spacer is disposed over the gate stack.

20. The TFET of claim 19 , further comprising a source contact that directly contacts the first doped region and the silicon-and-nitrogen containing spacer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• Kuo Cheng-Cheng
• Liu Chi-Wen
• Zhu Ming

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title