Method of producing large GaAs and GaP infrared windows

US12203191B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12203191-B2
Application numberUS-202218073228-A
CountryUS
Kind codeB2
Filing dateDec 1, 2022
Priority dateDec 1, 2022
Publication dateJan 21, 2025
Grant dateJan 21, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of growing large GaAs or GaP IR window slabs by HVPE, and in embodiments by LP-HVPE, includes obtaining a plurality of thin, single crystal, epitaxial-quality GaAs or GaP wafers, cleaving the wafers into tiles having ultra-flat, atomically smooth, substantially perpendicular edges, and then butting the tiles together to form an HVPE substrate larger than 4 inches for GaP, and larger than 8 inches or even 12 inches for GaAs. Subsequent HVPE growth causes the individual tiles to fuse by optical bonding into a large “tiled” single crystal wafer, while any defects nucleated at the tile boundaries are healed, causing the tiles to merge with themselves and with the slab with no physical boundaries, and no degradation in optical quality. A dopant such as Si can be added to the epitaxial gases during the final HVPE growth stage to produce EMI shielded GaAs windows.

First claim

Opening claim text (preview).

We claim: 1. A slab of GaAs having a largest dimension that is greater than eight inches or a slab of GaP having a largest dimension that is greater than four inches, the slab being suitable for forming an infrared (IR) transparent window, the slab being formed by the process: obtaining a plurality of epitaxial quality GaAs or GaP wafers; cleaving the wafers into tiles having cleaved edges; aligning the cleaved edges of the tiles on a substrate holder in intimate contact, optical bonding thereof thereby yielding a tiled GaAs substrate having a largest dimension that is greater than eight inches or a GaP substrate having a largest dimension that is greater than four inches; preparing an HVPE reactor having a reaction chamber that is sufficiently large to contain the tiled substrate and to apply gasses thereto; placing the substrate holder and tiled substrate into the reaction chamber of the HVPE reactor; applying a plurality of HVPE gases to a surface of the tiled substrate within the reaction chamber, such that at least two of the HVPE gases react with each other to form GaAs or GaP on the tiled substrate via HVPE, thereby causing a slab of GaAs to form on the tiled substrate having a largest dimension of greater than eight inches, or a slab of GaP having a largest dimension of greater than four inches; and growing the GaAs or GaP slab via the HVPE to a desired thickness by continuing to apply the gases to a surface of the slab. 2. The slab of GaAs or GaP of claim 1 , wherein any defects that are nucleated at the boundaries of the tiles are healed as the slab is grown via HVPE, causing the tiles to merge together with no physical boundaries between them and substantially no degradation in optical quality of the slab, thereby obviating any need to grind away the tiled substrate after the growing by HVPE has been completed. 3. The slab of GaAs or GaP of claim 1 , wherein cleaving the wafers includes cleaving the wafers along a (110) crystalline direction. 4. The slab of GaAs or GaP of claim 1 , wherein the slab is a slab of GaAs having a largest dimension of greater than 12 inches, or a slab of GaP having a largest dimension of greater than 8 inches. 5. The slab of GaAs or GaP of claim 1 , wherein a thickness of the slab is at least 2 mm. 6. The slab of GaAs or GaP of claim 1 , further comprising an electrically conductive layer of doped GaAs or GaP on the slab. 7. The slab of GaAs or GaP of claim 1 , further comprising an anti-reflective coating applied to at least one surface of the slab. 8. A method of producing a slab of GaAs or GaP, the slab being suitable for forming a GaAs infrared (IR) transparent window having a largest dimension that is greater than eight inches, or a GaP infrared (IR) transparent window having a largest dimension that is greater than four inches, the method comprising: obtaining a plurality of epitaxial quality GaAs or GaP wafers; cleaving the wafers into tiles having cleaved edges; aligning the cleaved edges of the tiles on a substrate holder in intimate contact, optical bonding thereof thereby yielding a GaAs tiled substrate having a largest dimension that is greater than eight inches, or a GaP tiled substrate having a largest dimension that is greater than four inches; preparing an HVPE reactor having a reaction chamber that is sufficiently large to contain the tiled substrate and to apply gasses thereto; placing the substrate holder and tiled substrate into the reaction chamber of the HVPE reactor; applying a plurality of HVPE gases to a surface of the tiled substrate within the reaction chamber, such that at least two of the HVPE gases react with each other to form GaAs or GaP on the tiled substrate via HVPE, thereby causing a slab of GaAs to form on the tiled substrate having a largest dimension of greater than eight inches, or a slab of GaP having a largest dimension of greater than four inches; and growing the GaAs or GaP slab via the HVPE to a desired thickness by continuing to apply the gases to a surface of the slab. 9. The method of claim 8 , wherein the method further includes heating the tiled substrate while applying a preliminary gas thereto prior to causing the slab of GaAs or GaP to form on the tiled substrate, said preliminary gas being flowing arsine if the tiled substrate is a GaAs substrate, or flowing phosphine if the tiled substrate is a GaP substrate. 10. The method of claim 8 , wherein obtaining the epitaxial quality GaAs or GaP wafers includes obtaining the wafers from a commercial source. 11. The method of claim 8 , wherein any defects that are nucleated at the boundaries of the tiles are healed as the slab is grown via HVPE, causing the tiles to merge together with no physical boundaries between them and substantially no degradation in optical quality of the slab, thereby obviating any need to grind away the tiled wafer after the growing by HVPE has been completed. 12. The method of claim 8 , wherein the HVPE is LP-HVPE. 13. The method of claim 8 , wherein cleaving the slices includes cleaving the slices along a (110) crystalline direction of the GaAs or GaP wafers. 14. The method of claim 8 , wherein the tiles are rectangular. 15. The method of claim 8 , wherein the tiles are parallelograms. 16. The method of claim 8 , wherein the slab is a slab of GaAs having a largest dimension of greater than 12 inches, or a slab of GaP having a largest dimension of greater than 8 inches. 17. The method of claim 8 , wherein the desired thickness is at least 2 mm. 18. The method of claim 17 , wherein a time required to grow the slab to the desired thickness is no greater than 1 week. 19. The method of claim 8 , further comprising, during a final phase of growing the slab, including a dopant gas as one of the gases that are applied to the surface of the slab, thereby forming an electrically conductive layer of doped GaAs or GaP on the slab. 20. The method of claim 19 , wherein the dopant gas contains silicon. 21. The method of claim 8 , further comprising applying a layer of doped GaAs or GaP to a surface of the slab after the slab has been removed from the HVPE reactor. 22. The method of claim 8 , wherein one of the HVPE gases is GaCl. 23. The method of claim 22 , wherein the GaCl is formed by reacting HCl gas with liquid Ga. 24. The method of claim 8 , wherein one of the HVPE gases is AsH 3 . 25. The method of claim 8 , wherein one of the HVPE gases is PH 3 . 26. The method of claim 8 , further comprising, after the slab has grown to the desired thickness, applying an anti-reflective coating to at least one surface of the slab.

Assignees

Inventors

Classifications

  • Gallium phosphide · CPC title

  • by contacting with diffusion material in the gaseous state · CPC title

  • Joining of crystals · CPC title

  • C30B29/42Primary

    Gallium arsenide · CPC title

  • C30B25/186Primary

    being specially pre-treated by, e.g. chemical or physical means · CPC title

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What does patent US12203191B2 cover?
A method of growing large GaAs or GaP IR window slabs by HVPE, and in embodiments by LP-HVPE, includes obtaining a plurality of thin, single crystal, epitaxial-quality GaAs or GaP wafers, cleaving the wafers into tiles having ultra-flat, atomically smooth, substantially perpendicular edges, and then butting the tiles together to form an HVPE substrate larger than 4 inches for GaP, and larger th…
Who is the assignee on this patent?
Bae Sys Inf & Elect Sys Integ
What technology area does this patent fall under?
Primary CPC classification C30B29/42. Mapped technology areas include Chemistry & Metallurgy.
When was this patent published?
Publication date Tue Jan 21 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).