Ultra long lifetime gallium arsenide

Patent metadata

Field	Value
Publication number	US-10156023-B2
Application number	US-201715474139-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Jun 11, 2013
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A system and method for producing bulk GaAs with an increased carrier lifetime of at least 10 microseconds is provided. The system and method of producing the GaAs crystal involves using a technique called low pressure hydride vapor phase epitaxy (LP-HVPE). In this technique, a gas containing Ga (typically GaCl) is reacted with a gas containing As (typically AsH3) at the surface of a GaAs substrate. When grown under the proper conditions, the epitaxial, vapor grown GaAs crystal has ultra-long free carrier lifetimes of at least one order of magnitude greater than that of the previous lifetime of 1 microsecond. This very long free carrier lifetime GaAs will be particularly useful as a semiconductor radiation detector material and is also expected to be useful for many other applications than include medical imaging, solar cells, diode lasers, and optical limiters and other applications.

First claim

What is claimed is:

1. A method of forming bulk gallium arsenide (GaAs) having a carrier lifetime of at least 10 microseconds comprising:
providing a low-pressure hydride vapor epitaxy (HVPE) system including a reaction chamber;
providing an arsine source;
providing a gallium chloride source;
delivering arsine (AsH3) from the arsine source to a substrate inside the reaction chamber;
delivering gallium chloride (GaCl) from the gallium chloride source to the substrate;
delivering AsH3 orthogonally relative to the GaCl directly at the substrate surface; and
mixing and effecting a reaction of the gallium chloride with the arsine directly at the substrate surface to create bulk GaAs having a carrier lifetime of at least 10 microseconds.

2. The method of claim 1 , wherein mixing and effecting the reaction of the gallium chloride with the arsine directly at the substrate surface is accomplished by a close-coupled shower-head apparatus delivering the gallium chloride to mix with arsine flowing across the wafer surface.

3. The method of claim 1 , further comprising:
growing bulk GaAs to a thickness greater than 500 micrometers.

4. The method of claim 1 , wherein the substrate is an off-cut semiconductor substrate wafer, wherein an off-cut angle, relative to a primary crystallographic axis is greater than 1° .

5. The method of claim 4 , wherein the off-cut angle is in a range from 1° to 10° .

6. The method of claim 5 , wherein the off-cut angle is about 4° .

7. The method of claim 1 , further comprising:
precluding growth of parasitic Gallium Arsenide (GaAs) deposits on chamber walls of the low pressure HVPE system through direct delivery of gallium chloride via a close-coupled shower-head apparatus to react with arsine flowing across the wafer surface.

8. The method of claim 1 , further comprising:
minimizing the incorporation of Silicon (Si) and Oxygen (O) impurities to effectuate the long carrier lifetimes.

9. The method of claim 8 , further comprising:
precluding flow of hydrogen chloride (HCl) along silicon dioxide (SiO 2 ) chamber walls of the low pressure HVPE system.

10. The method of claim 8 , further comprising:
replacing silicon dioxide (SiO 2 ) with Pyrolytic Boron Nitride (PBN) in a main reaction zone of the reaction chamber of the low pressure HVPE system.

11. The method of claim 10 , wherein a shower-head apparatus delivering the gallium chloride to react with arsine at the substrate surface is fabricated from PBN.

12. The method of claim 10 , wherein a susceptor is covered by PBN.

13. The method of claim 10 , further comprising:
rotating a satellite disc that supports a wafer holder and wafer from below, wherein the wafer holder is fabricated from PBN.

14. The method of claim 1 , further comprising providing a recessed horizontal wafer holder.

15. The method of claim 14 , wherein the recessed horizontal wafer holder reduces back-side impurity vapor transport from the substrate.

16. The method of claim 1 , further comprising:
rotating the substrate, wherein the substrate is rotated during GaAs growth.

17. The method of claim 16 , wherein the wafer is rotated to enhance mixing of the reacting GaCI and AsH 3 gases.

18. The method of claim 16 , wherein the wafer is rotated to achieve bulk GaAs with uniform composition and thickness.

19. The method of claim 16 , wherein the wafer is rotated by flowing inert gas over grooves on the underside of the satellite disc that supports the wafer.

Assignees

• Bae Sys Inf & Elect Sys Integ

Inventors

• Schunemann Peter G
• Zawilski Kevin T

Classifications

• C30B29/42

  Gallium arsenide · CPC title

• C30B25/12

  Substrate holders or susceptors · CPC title

• C30B25/14 Primary

  Feed and outlet means for the gases; Modifying the flow of the reactive gases · CPC title

• H01L31/0304

  Electricity · mapped topic

• H10F77/124

  comprising only Group III-V materials, e.g. GaAs · CPC title