Semiconductor device having uniform multi-package antenna array and method of manufacture

Patent metadata

Field	Value
Publication number	US-12199333-B2
Application number	US-202217649725-A
Country	US
Kind code	B2
Filing date	Feb 2, 2022
Priority date	Feb 15, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A semiconductor device comprising a substrate, a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array having a uniform pitch, and a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array having a uniform pitch. The second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch. Also provided is a method of manufacturing a multi-package module and a method of providing package-to-package grounding.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a substrate;
a first integrated circuit package mounted on the substrate, the first integrated circuit package comprising a first antenna sub-array, wherein the first antenna sub-array has a uniform pitch;
a second integrated circuit package mounted on the substrate, the second integrated circuit package comprising a second antenna sub-array, wherein the second antenna sub-array has a uniform pitch;
wherein the second integrated circuit package is mounted adjacent to the first integrated circuit package to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch that is the same as the pitch of the first antenna sub-array and the second antenna sub-array,
wherein the first integrated circuit package is connected to the second integrated circuit package on the substrate by a joint,
wherein the joint is configured to provide grounding or an electrical connection between the first integrated circuit package and the second integrated circuit package,
wherein the joint comprises an upper portion and a lower portion,
wherein the upper portion is disposed between the first antenna sub-array and the second antenna sub-array and comprises an electrically conductive material, and
wherein the lower portion is disposed adjacent to the substrate and comprises an electrically insulating material.

2. The semiconductor device of claim 1 , wherein the antenna array comprises a plurality of antenna elements and each of the plurality of antenna elements are the same size and shape.

3. The semiconductor device of claim 1 , wherein there is a gap between the first integrated circuit package and the second integrated circuit package when mounted on the substrate.

4. The semiconductor device of claim 1 , wherein the first integrated circuit package and the second integrated circuit package are integrally formed.

5. The semiconductor device of claim 1 ,
wherein the multi-package module is formed of at least three integrated circuit packages positioned adjacent to each other, each integrated circuit package comprising a sub-array that has a uniform pitch.

6. The semiconductor device of claim 2 , wherein there is a gap between the first integrated circuit package and the second integrated circuit package when mounted on the substrate.

7. The semiconductor device of claim 1 , further comprising a plurality of multi-package modules, wherein the multi-package modules are mounted adjacent to each other on the substrate.

8. A method of manufacturing a semiconductor device, comprising:
providing a first integrated circuit package comprising a first antenna sub-array, wherein the first antenna sub-array has a uniform pitch;
providing a second integrated circuit package comprising a second antenna sub-array, wherein the second antenna sub-array has a uniform pitch;
positioning the second integrated circuit package adjacent to the first integrated circuit package on a substrate to form a multi-package module having an antenna array formed of the first antenna sub-array and the second antenna sub-array, wherein the antenna array has a uniform pitch that is the same as the pitch of the first antenna sub-array and the second antenna sub-array;
mounting the first integrated circuit package and the second integrated circuit package on the substrate, wherein there is a gap between the first integrated circuit and the second integrated circuit package when mounted on the substrate; and
providing grounding or an electrical connection between the first integrated circuit package and the second integrated circuit package by:
inserting an electrically insulating material into a lower portion of the gap disposed adjacent to the substrate; and
inserting an electrically conductive material into an upper portion of the gap between the first antenna sub-array and the second antenna sub-array.

9. The method of claim 8 , wherein positioning the second integrated circuit package adjacent to the first integrated circuit package comprises:
minimising the gap between the first integrated circuit package and the second integrated circuit package; and/or
rotating the second integrated circuit package relative to the first integrated circuit package.

10. The method of claim 8 , further comprising cutting the first integrated circuit package and/or the second integrated circuit package to ensure that the antenna array of the multi-package module has a uniform pitch.

11. The method of claim 10 , wherein the cutting step comprises cutting off an end portion of the first integrated circuit package and cutting off an end portion of the second integrated circuit package; and/or
wherein the first antenna sub-array and the second antenna sub-array each comprise a grid of antenna elements separated by shielding walls, and the cutting step comprises cutting through the first integrated circuit package and the second integrated circuit package lengthwise along one of the shielding walls.

12. The method of claim 8 , wherein providing grounding between the first integrated circuit package and the second integrated circuit package comprises expanding the upper portion of the gap by making a partial or step cut in the first and second integrated circuit packages.

13. The method of claim 8 , further comprising:
positioning at least a third integrated circuit package adjacent to the first integrated circuit package or the second integrated circuit package on the substrate, such that the multi-package module is formed of at least three integrated circuit packages; and/or
forming a plurality of multi-packages modules as defined in any preceding claim and mounting the multi-packages modules adjacent to each other on the substrate.

14. The method of claim 9 , further comprising cutting the first integrated circuit package and/or the second integrated circuit package to ensure that the antenna array of the multi-package module has a uniform pitch.

Assignees

• Nxp Bv

Inventors

• Kamphuis Antonius Hendrikus Jozef
• Bergman Jan Willem
• Geurts Marcellinus Johannes Maria
• Acar Mustafa
• Mattheijssen Paul
• Mandamparambil Rajesh
• Damian Andrei-Alexandru
• Mavinkurve Amar Ashok

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W44/248

  for antennas · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title