Systems and methods for inter-chip communication

Patent metadata

Field	Value
Publication number	US-9633976-B1
Application number	US-201314090993-A
Country	US
Kind code	B1
Filing date	Nov 26, 2013
Priority date	Sep 4, 2003
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.

First claim

We claim:

1. A quilt packaging system comprising:
a first electronic device comprising, a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon; and
a second electronic device comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect nodules disposed thereon,
wherein the first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and
wherein at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.

2. A quilt packaging system as defined in claim 1 , wherein the at least one interconnect nodule disposed on the first edge surfaces of the first and second electronic devices each protrude from the respective first edge surfaces.

3. A quilt packaging system as defined in claim 1 , wherein at least one of the one or more interconnect nodules of the first electronic device is deformable.

4. A quilt packaging system as defined in claim 1 , wherein the first electronic device is positioned in a first plane, and wherein the second electronic device is positioned co-planar and adjacent to the first electronic device.

5. A quilt packaging system as defined in claim 1 , wherein the first electronic device is positioned in a first plane, and wherein the second electronic device is positioned in a second plane.

6. A quilt packaging system as defined in claim 1 , further comprising:
a third electronic device comprising a plurality of edge surface at least a first edge surface of which comprises one or more interconnect nodules disposed thereon, and
wherein at least one of the one or more interconnect nodules of the third electronic device is configured to be electrically connected to at least one of the one or more interconnect nodules of the first electronic device.

7. A quilt packaging system as defined in claim 1 , further comprising:
a female alignment element disposed on the interconnect nodule of the first electronic device; and
a male alignment element, disposed on the interconnect nodule of the second electronic device, configured to be inserted into the female alignment element to align the at least one interconnect module disposed on the first edge surface of the first electronic device with the at least one interconnect nodule disposed on the first edge surface of the second electronic device.

8. A quilt packaging system as defined in claim 1 , wherein the electrical connection is a conductive coupling between the first and second electrical devices.

9. A quilt packaging system as defined in claim 1 , wherein the electrical connection between the first and second electrical devices further includes the use of solder material.

10. A quilt packaging system as defined in claim 1 , wherein the interconnect nodules comprise a conductive material with an overlay of a flowable solder material.

11. A quilt packaging system as defined in claim 1 , wherein the electrical connection between the first and second electrical devices further includes the use of at least one of a thermomechanical, ultrasonic bonding, heat welding, or laser welding technique.

12. A quilt packaging system as defined in claim 1 , wherein the first and second electronic devices is constructed of a different semiconductor material.

13. A quilt packaging system as defined in claim 12 , wherein the different semiconductor materials include at least one of a silicon-based or compound-based III-V, II-VI, or IV-IV semiconductors.

14. A quilt packaging system as defined in claim 1 , wherein the first and second electronic devices have different functions within an architecture of the quilt packaging system.

15. A quilt packaging system as defined in claim 14 , wherein the function of the first and second electronic devices is at least one of:
a baseband processor,
a power amplifier,
a RF signal processor,
an audio amplifier,
a central processing unit,
an input/output device,
a video graphics processor, or
a memory storage device.

16. A quilt packaging system as defined in claim 1 , wherein one of the second electronic device or the first electronic device is an interposer.

17. A quilt packaging system as defined in claim 16 , wherein the interposer is a conductive material.

18. A quilt packaging system as defined in claim 17 , wherein the conductive material is solder.

Assignees

• Univ Notre Dame Du Lac

Inventors

• Bernstein Gary H
• Fay Patrick
• Porod Wolfgang
• Liu Qing

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/284

  characterised by structural arrangements for measuring or testing · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/07235

  Applying EM radiation, e.g. induction heating or using a laser · CPC title

• H10W72/07227

  involving guiding structures, e.g. spacers or supporting members · CPC title