Multi-chip detector appratus

Patent metadata

Field	Value
Publication number	US-10930620-B2
Application number	US-201916505908-A
Country	US
Kind code	B2
Filing date	Jul 9, 2019
Priority date	Aug 1, 2018
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.

First claim

What is claimed is:

1. A multi-chip detector apparatus having a plurality of single chips arranged in inter-chip connection on a substrate, the multi-chip detector apparatus comprising:
a first single chip having a plurality of single detectors formed in m rows and n columns, said m and n being natural numbers;
a second single chip positioned at either one of a left side and a right side of the first single chip, the second single chip connected row-wise with the first single chip; and
a third single chip positioned at either one of an upper side and a lower side of the first single chip, the third single chip connected column-wise with the first single chip,
wherein the second single chip and the third single chip also have a plurality of single detectors formed in m rows and n columns,
wherein the first single chip further comprises:
a switch control line formed in either one of a column direction and a row direction in which the plurality of single detectors are arranged, the switch control line connected with single detectors of a corresponding column or a corresponding row;
a signal line formed in a direction different from a direction in which the switch control line is formed, the signal line formed corresponding to each column or each row of an arrangement of the plurality of single detectors;
a row selection switch connected with either one of a left end and a right end of the signal line formed for each row; and
a ground pad formed at an opposite end of the row selection switch, and
wherein a switch control pad of the first single chip is connected with a ground pad of the second single chip.

2. The multi-chip detector apparatus of claim 1 , wherein a first outermost single detector and a second outermost single detector present within a same single chip have a pad arranged in-between in a column direction or a row direction for inter-chip connection.

Assignees

• Univ Korea Res & Bus Found

Inventors

• Rieh Jae-Sung
• Song Ki Ryong
• Cho Jai Heon
• Kim Doyoon

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W44/248

  for antennas · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title