Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12199164-B2
Application number	US-202318306168-A
Country	US
Kind code	B2
Filing date	Apr 24, 2023
Priority date	Nov 30, 2017
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin, the gate structure comprising: a first metallic layer; a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element; and an oxide layer between the first metallic layer and the second metallic layer.

First claim

What is claimed is:

1. A method, comprising:
forming a semiconductor fin over a substrate;
forming a gate structure over the semiconductor fin, the gate structure comprising:
a first metallic layer;
a second metallic layer over the first metallic layer, wherein the first metallic layer is a metal compound of a first element and a second element and the second metallic layer is a single-element metal of the second element;
an oxide layer between the first metallic layer and the second metallic layer; and
a third metallic layer over the oxide layer, wherein the third metallic layer has a same composition as the first metallic layer.

2. The method of claim 1 , wherein the oxide layer is an oxide of the first metallic layer.

3. The method of claim 1 , further comprising forming source/drain epitaxy structures over the semiconductor fin, wherein the gate structure is between the source/drain epitaxy structures.

4. The method of claim 1 , wherein the first element and the second element comprise Hf, Ti, Ta, W, Si, Co, Mo, N, O, So, Ge, P, B, Ga, As, La, Al, Cu, or S.

5. The method of claim 1 , wherein a thickness of the oxide layer is in a range from about 5 Å to about 30 Å.

6. The method of claim 1 , wherein a thickness of one of the first metallic layer, the second metallic layer, and the third metallic layer is in a range from about 5 Å to about 15 Å.

7. The method of claim 1 , wherein the gate structure further comprises a gate dielectric layer below the first metallic layer.

8. The method of claim 1 , wherein the gate structure further comprises a gate electrode over the third metallic layer.

9. A method, comprising:
forming a semiconductor fin over a substrate;
forming source/drain epitaxy structures over the semiconductor fin;
forming a gate structure over a region of the semiconductor fin between the source/drain epitaxy structures, wherein forming the gate structure comprises:
forming a first metallic layer over the semiconductor fin, wherein the first metallic layer comprises more than one metal element;
oxidizing a surface layer of the first metallic layer to form an oxide of the first metallic layer over the first metallic layer; and
forming a second metallic layer over the oxide of the first metallic layer.

10. The method of claim 9 , wherein forming the gate structure further comprises forming a third metallic layer over the semiconductor fin prior to forming the first metallic layer, wherein the third metallic layer has a different composition than the first metallic layer.

11. The method of claim 9 , wherein forming the gate structure further comprises forming a third metallic layer over the second metallic layer, wherein the third metallic layer has a different composition than the second metallic layer.

12. The method of claim 9 , wherein the oxide of the first metallic layer has a thickness in a range from about 5 Å to about 30 Å.

13. The method of claim 9 , wherein the oxide of the first metallic layer has a U-shape cross-sectional profile.

14. The method of claim 9 , wherein a thickness of the first metallic layer or a thickness of the second metallic layer is in a range from about 5 Å to about 15 Å.

15. The method of claim 8 , wherein forming the gate structure further comprises forming a gate electrode over the second metallic layer.

16. A method, comprising:
forming a semiconductor fin over a substrate;
forming source/drain regions over the semiconductor fin; and
forming a gate structure between the source/drain regions, wherein the gate structure comprises a stack of alternating first metallic layers and second metallic layers, wherein the first metallic layers have a composition of X a1 Y 1-a1 and the second metallic layers have a composition of X a2 Y 1-a2 , a1≠a2, and a1+a2=1.

17. The method of claim 16 , wherein each of the first and second metallic layers has a U-shape cross-section.

18. The method of claim 16 , wherein a thickness of one of the first and second metallic layers is in a range from about 5 Å to about 15 Å.

19. The method of claim 16 , wherein the gate structure further comprises a gate dielectric layer under the stack of alternating first metallic layers and second metallic layers.

20. The method of claim 16 , wherein the gate structure further comprises a gate structure over the stack of alternating first metallic layers and second metallic layers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiang Hsin-Che
• Tzeng Ju-Yuan
• Liang Chun-Sheng
• Yeh Chih-Yang
• Wang Shu-Hui
• Yeh Jeng-Ya David

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/44

  Conductive materials thereof · CPC title