Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Patent metadata

Field	Value
Publication number	US-9490255-B1
Application number	US-201514955443-A
Country	US
Kind code	B1
Filing date	Dec 1, 2015
Priority date	Dec 1, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

First claim

The invention claimed is:

1. An electrical device comprising:
a semiconductor substrate having an n-type region, a p-type region and a mid gap region;
a p-type semiconductor device present in the p-type region having a p-type work function gate structure comprised of a first high-k gate dielectric, a first metal containing buffer layer present on the first high-k gate dielectric, and a first titanium nitride layer having a first thickness present on the first metal containing buffer layer;
a mid gap semiconductor device present in the mid gap region of the semiconductor substrate having a mid gap gate structure comprised of a second high-k gate dielectric, a second metal containing buffer layer present on the second high-k gate dielectric, and a second titanium nitride layer having a second thickness that is less than the first thickness present on the second metal containing buffer layer; wherein the mid gap semiconductor device has a gate work function ranging from 4.5 eV to 4.6 eV, and
an n-type semiconductor device present in the n-type region having an n-type work function gate structure comprised of a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a n-type gate conductor contact present atop the third metal containing buffer layer.

2. The electrical device of claim 1 , wherein the p-type semiconductor device further comprises a p-type gate conductor contact present on the first titanium nitride layer, and the mid gap semiconductor device further comprises a mid gap gate conductor contact present on the second titanium nitride layer.

3. The electrical device of claim 1 , wherein the n-type gate conductor contact is in direct contact with the third metal containing buffer layer.

4. The electrical device of claim 1 further comprising a third titanium nitride layer having a third thickness that is less than the second thickness, the third titanium nitride layer present on the third metal containing buffer layer, wherein the n-type gate conductor contact is in direct contact with the third titanium nitride layer.

5. The electrical device of claim 1 , wherein the p-type semiconductor device is a p-type FinFET, the mid gap semiconductor device is a mid gap FinFET, and the n-type semiconductor device is an n-type FinFET.

6. The electrical device of claim 1 , wherein the p-type semiconductor device is a planar p-type FET, the mid gap semiconductor device is a planar mid gap FET, and the n-type semiconductor device is planar n-type FET.

7. The electrical device of claim 6 , wherein the semiconductor substrate is a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a extremely thin semiconductor on insulator (ETSOI) substrate, or a combination thereof.

8. The electrical device of claim 1 , wherein at least one of the first metal containing buffer layer, the second metal containing buffer layer and the third metal containing buffer layer comprises tantalum nitride (TaN).

9. The electrical device of claim 1 , wherein the first metal containing buffer layer, the second metal containing buffer layer and the third metal containing buffer layer have a same composition.

10. The electrical device of claim 1 , wherein at least one of the first high-k gate dielectric, the second high-k gate dielectric, and the third high-k gate dielectric comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, nitrided hafnium silicate (HfSiON), lanthanum oxide (La 3 O 2 ), zirconium silicate (ZrSiOx) or a combination thereof.

11. An electrical device comprising:
a semiconductor substrate having an n-type region, a p-type region and a mid gap region;
a p-type semiconductor device present in the p-type region having a p-type work function gate structure comprised of a first high-k gate dielectric, a first metal containing buffer layer present on the first high-k gate dielectric, and a first titanium nitride layer having a first thickness present on the first metal containing buffer layer;
a mid gap semiconductor device present in the mid gap region of the semiconductor substrate having a mid gap gate structure comprised of a second high-k gate dielectric, a second metal containing buffer layer present on the second high-k gate dielectric, and a second titanium nitride layer having a second thickness that is less than the first thickness present on the second metal containing buffer layer; wherein the mid gap semiconductor device has a gate work function ranging from 4.5 eV to 4.6 eV, and
an n-type semiconductor device present in the n-type region having an n-type work function gate structure comprised of a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric, and a third titanium nitride layer present on the third metal containing buffer layer having a third thickness less than the second thickness.

12. The electrical device of claim 11 , wherein the p-type semiconductor device further comprises a first gate conductor contact present on the first titanium nitride layer, the mid gap semiconductor device further comprises a second gate conductor contact present on the second titanium nitride layer, and the n-type semiconductor device further comprises a third gate conductor contact present on the third titanium nitride layer.

13. The electrical device of claim 11 , wherein the p-type semiconductor device is a p-type FinFET, the mid gap semiconductor device is a mid gap FinFET, and the n-type semiconductor device is an n-type FinFET, or the p-type semiconductor device is a planar p-type FET, the mid gap semiconductor device is a planar mid gap FET, and the n-type semiconductor device is planar n-type FET.

14. The electrical device of claim 11 , wherein at least one of the first metal containing buffer layer, the second metal containing buffer layer and the third metal containing buffer layer comprises tantalum nitride (TaN).

15. A method of forming a semiconductor device comprising:
providing a semiconductor substrate having an n-type region, a p-type region and a mid gap region;
forming a p-type semiconductor device in the p-type region having a p-type work function gate structure comprised of a first high-k gate dielectric, a first metal containing buffer layer present on the first high-k gate dielectric, and a first titanium nitride layer having a first thickness present on the first metal containing buffer layer;
forming a mid gap semiconductor device in the mid gap region of the semiconductor substrate having a mid gap gate structure comprised of a second high-k gate dielectric, a second metal containing buffer layer present on the second high-k gate dielectric, and a second titanium nitride layer having a second thickness that is less than the first thickness present on the second metal containing buffer layer; wherein the mid gap semiconductor device has a gate work function ranging from 4.5 eV to 4.6 eV, and
forming an n-type semiconductor device in the n-type region having an n-type work function gate structure comprised of a third high-k gate dielectric; a third metal containing buffer layer on the third high-k gate dielectric, and a n-type gate conductor contact present on the third metal containing buffer layer.

Assignees

• IBM

Inventors

• Edge Lisa F
• Jagannathan Hemanth
• Jamison Paul C
• Paruchuri Vamsi K

Classifications

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0188

  Manufacturing their isolation regions · CPC title