Block layer in the metal gate of MOS devices

Patent metadata

Field	Value
Publication number	US-9735231-B2
Application number	US-201414231099-A
Country	US
Kind code	B2
Filing date	Mar 31, 2014
Priority date	Mar 31, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.

First claim

What is claimed is:

1. A method comprising:
forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer;
removing the dummy gate stack to form a recess;
forming a gate dielectric layer in the recess;
forming a metal layer in the recess and over the gate dielectric layer, wherein the metal layer has an n-work function, and the metal layer provides work function of a respective gate stack comprising the gate dielectric layer and the metal layer;
forming a block layer over the metal layer using Atomic Layer Deposition (ALD); and
filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.

2. The method of claim 1 , wherein the forming the metal layer comprises depositing a titanium aluminum (TiAl) layer, and wherein the forming the block layer comprises forming a Cobalt tungsten (CoW) layer.

3. The method of claim 1 , wherein the block layer is in contact with the metal layer, and wherein the method further comprises forming a cobalt layer over and contacting the block layer.

4. The method of claim 3 , wherein the forming the cobalt layer is performed using ALD.

5. The method of claim 3 , wherein the forming the block layer is performed using precursors comprising:
a cobalt-containing precursor; and
a tungsten-containing precursor, wherein the forming the cobalt layer is performed in situ with the block layer in a same production tool, and wherein the forming the cobalt layer comprises:
turning off the tungsten-containing precursor; and
continuing conducting the cobalt-containing precursor into the same production tool.

6. The method of claim 1 , wherein the filling the remaining portion of the recess with the metallic materials comprises depositing an aluminum layer over the block layer.

7. The method of claim 1 further comprising, after the forming the gate dielectric layer and before the forming the metal layer:
forming a titanium nitride layer over the gate dielectric layer;
forming a tantalum nitride layer over the titanium nitride layer; and
forming an additional titanium nitride layer over the tantalum nitride layer.

8. A method comprising:
forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer;
removing the dummy gate stack to form a recess in an inter-layer dielectric;
forming a gate dielectric layer in the recess;
forming a titanium aluminum layer in the recess;
forming a cobalt tungsten layer over the titanium aluminum layer;
forming a cobalt layer over the cobalt tungsten layer, the cobalt tungsten layer being interposed between the cobalt layer and the titanium aluminum layer;
filling remaining portions of the recess with metallic materials; and
performing a planarization to remove excess portions of the metallic materials, the cobalt layer, the cobalt tungsten layer, the titanium aluminum layer, and the gate dielectric layer, with the excess portions being over the recess.

9. The method of claim 8 , wherein the forming the cobalt tungsten layer comprises an atomic layer deposition.

10. The method of claim 8 , wherein the forming the cobalt layer comprises an atomic layer deposition.

11. The method of claim 8 , wherein the forming the cobalt tungsten layer comprises an atomic layer deposition using precursors comprising:
a cobalt-containing precursor; and
a tungsten-containing precursor, wherein the forming the cobalt layer is performed in situ with the cobalt tungsten layer in a same production tool, and wherein the forming the cobalt layer comprises the atomic layer deposition, and comprises:
turning off the tungsten-containing precursor; and
continuing conducting the cobalt-containing precursor into the same production tool.

12. The method of claim 8 , wherein the cobalt tungsten layer is in contact with the titanium aluminum layer, and wherein the cobalt layer is in contact with the cobalt tungsten layer.

13. The method of claim 8 further comprising:
forming a contact etch stop layer overlying the dummy gate stack;
forming the inter-layer dielectric over the contact etch stop layer; and
performing a planarization to remove excess portions of the contact etch stop layer and the inter-layer dielectric, wherein the excess portions are over the dummy gate stack.

14. The method of claim 8 , wherein the filling the remaining portions of the recess with the metallic materials comprises forming an aluminum layer over the cobalt layer.

15. The method of claim 8 further comprising, after the forming the gate dielectric layer and before the forming the titanium aluminum layer:
forming a titanium nitride layer over the gate dielectric layer;
forming a tantalum nitride layer over the titanium nitride layer; and
forming an additional titanium nitride layer over the tantalum nitride layer.

16. A method comprising:
removing a dummy gate stack to form a recess in an inter-layer dielectric, wherein a semiconductor fin is exposed, and is located in the recess;
forming a gate dielectric layer on a top surface and a sidewall of the semiconductor fin;
depositing a titanium aluminum layer over the gate dielectric layer;
depositing a cobalt tungsten layer over and contacting the titanium aluminum layer using Atomic Layer Deposition (ALD);
depositing a cobalt layer over and contacting the cobalt tungsten layer using ALD, the cobalt tungsten layer being interposed between the cobalt layer and the titanium aluminum layer;
filling remaining portions of the recess with metallic materials; and
performing a planarization on the metallic materials, the cobalt layer, the cobalt tungsten layer, the titanium aluminum layer, and the gate dielectric layer.

17. The method of claim 16 , wherein the cobalt tungsten layer is formed using precursors comprising:
a cobalt-containing precursor; and
a tungsten-containing precursor, wherein the forming the cobalt layer is performed in situ with the cobalt tungsten layer in a same production tool, and the cobalt layer is formed by:
turning off the tungsten-containing precursor; and
continuing conducting the cobalt-containing precursor into the same production tool.

18. The method of claim 16 further comprising:
forming a contact etch stop layer overlying the dummy gate stack;
forming the inter-layer dielectric over the contact etch stop layer; and
performing a planarization to remove excess portions of the contact etch stop layer and the inter-layer dielectric, wherein the excess portions are over the dummy gate stack.

19. The method of claim 16 , wherein the filling the remaining portions of the recess with the metallic materials comprises forming an aluminum layer over the cobalt layer.

20. The method of claim 16 further comprising, after the forming the gate dielectric layer and before the depositing the titanium aluminum layer:
forming a titanium nitride layer over the gate dielectric layer; and
forming a tantalum nitride layer over the titanium nitride layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsao Jung-Chih
• Hung Chi-Cheng
• Wang Yu-Sheng
• Lee Wen-Hsi
• Chen Kei-Wei
• Wang Ying-Lang

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/669

  the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H01L29/66553

  Electricity · mapped topic

• H01L29/7834

  Electricity · mapped topic