Structure and method for an SRAM circuit

Patent metadata

Field	Value
Publication number	US-9640540-B1
Application number	US-201615213542-A
Country	US
Kind code	B1
Filing date	Jul 19, 2016
Priority date	Jul 19, 2016
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

An integrated circuit includes first and second SRAM cells. The first SRAM cell includes first and second pull-up devices, first and second pull-down devices configured with the first and second pull-up devices to form first and second cross-coupled inverters, first and second pass-gate devices configured with the first and second cross-coupled inverters for writing data, a read pull-down device coupled to the first inverter, and a read pass-gate device coupled to the read pull-down device. The second SRAM cell includes third and fourth pull-up devices, and third and fourth pull-down devices configured with the third and fourth pull-up devices to form third and fourth cross-coupled inverters. Work function layers of gates of the first pull-up device, first pull-down device, and third pull-up device have a first work function, a second work function, and a third work function respectively. The first, second, and third work functions are different from each other.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first static random access memory (SRAM) cell in a semiconductor substrate, wherein the first SRAM cell includes:
first and second pull-up devices;
first and second pull-down devices configured with the first and second pull-up devices to form first and second cross-coupled inverters for data storage;
first and second pass-gate devices configured with the first and second cross-coupled inverters for writing data;
a read pull-down device coupled to the first inverter; and
a read pass-gate device coupled to the read pull-down device for reading data;

a second SRAM cell in the semiconductor substrate, wherein the second SRAM cell includes:
third and fourth pull-up devices;
third and fourth pull-down devices configured with the third and fourth pull-up devices to form third and fourth cross-coupled inverters for data storage;
third and fourth pass-gate devices configured with the two cross-coupled inverters for data access;
wherein a gate of the first pull-up device includes a first work function layer having a first work function;
wherein a gate of the first pull-down device includes a second work function layer having a second work function different from the first work function; and
wherein a gate of the third pull-up device includes a third work function layer having a third work function different from the first and second work functions.

2. The integrated circuit of claim 1 , where a gate of the third pull-down device includes a work function layer having the second work function.

3. The integrated circuit of claim 1 , wherein the first SRAM cell includes a contiguous gate structure including the gate of the first pull-up device, the gate of the first pull-down device, and a gate of the read pull-down device; and
wherein the gate of the read pull-down device includes a fourth work function layer including a fourth work function different from the first, second, and third work functions.

4. The integrated circuit of claim 3 , wherein a gate of the third pull-down device includes a fifth work function layer having a fifth work-function different from the first, second, third, and fourth work functions.

5. The integrated circuit of claim 3 , wherein the first pull-down device has a first pull-down device threshold voltage,
wherein the read pull-down device has a read pull-down device threshold voltage, and
wherein the first pull-down device threshold voltage is greater than the read pull-down device threshold voltage by at least about 40 millivolts (mV).

6. The integrated circuit of claim 1 , wherein the gate of the first pull-up device includes a first high-k dielectric material, and
wherein the gate of the third pull-up device includes a second high-k dielectric material substantially the same as the first high-k dielectric material.

7. The integrated circuit of claim 1 , wherein the first, second, third, and fourth pull-up devices are p-type fin-like field-effect transistors (pFinFETs), and
wherein the first, second, third, and fourth pull-down devices, the first, second, third, and fourth pass-gate devices, the read pass-gate device, and the read pull-down device are n-type FinFETs (nFinFETs).

8. The integrated circuit of claim 1 , wherein the first SRAM cell includes a write assist circuitry including a word-line voltage boost generator electrically connected to the first and second pass-gate devices.

9. The integrated circuit of claim 1 , wherein the first pull-up device has a first pull-up device threshold voltage,
wherein the third pull-up device has a third pull-up device threshold voltage, and
wherein the third pull-up device threshold voltage is greater than the first pull-up device threshold voltage by at least about 40 mV.

10. An integrated circuit, comprising:
a first static random access memory (SRAM) cell in a semiconductor substrate, wherein the first SRAM cell includes a write port portion and a read port portion, wherein the write port portion includes:
first and second pull-up devices; and
first and second pull-down devices configured with the first and second pull-up devices to form first and second cross-coupled inverters for data storage;

a second SRAM cell in the semiconductor substrate, wherein the second SRAM cell includes:
third and fourth pull-up devices; and
third and fourth pull-down devices configured with the third and fourth pull-up devices to form third and fourth cross-coupled inverters for data storage;

wherein a gate of the first pull-up device includes a first work function layer having a first work function;
wherein a gate of the first pull-down device includes a second work function layer having a second work function different from the first work function;
wherein a gate of the third pull-up device includes a third work function layer having a third work function different from the first and second work functions; and
wherein a gate of the third pull-down device includes a fourth work function layer having a fourth work function different from the first, second, and third work functions.

11. The integrated circuit of claim 10 , wherein the first work function layer includes a plurality of work function sub-layers.

12. The integrated circuit of claim 11 , wherein the gate of the first pull-up device includes a first high-k dielectric material, and
wherein the gate of the third pull-up device includes a second high-k dielectric material approximately the same as the first high-k dielectric material.

13. The integrated circuit of claim 11 , wherein the first, second, third, and fourth pull-up devices are p-type fin-like field-effect transistors (pFinFETs), and
wherein the first, second, third, and fourth pull-down device are n-type FinFETs (nFinFETs).

14. The integrated circuit of claim 11 , wherein the write port portion of the first SRAM cell includes:
first and second pass-gate devices first and second pass-gate devices coupled with the first and second cross-coupled inverters; and
a write assist circuitry including a word-line voltage boost generator electrically connected to the first and second pass-gate devices.

15. The integrated circuit of claim 11 , wherein the first pull-up device has a first pull-up device threshold voltage,
wherein the third pull-up device has a third pull-up device threshold voltage, and
wherein the third pull-up device threshold voltage is greater than the first pull-up device threshold voltage by at least about 40 mV.

16. The integrated circuit of claim 11 , wherein the first pull-down device has a first pull-down device threshold voltage,
wherein the third pull-down device has a third pull-down device threshold voltage, and
wherein the third pull-down device threshold voltage is greater than the first pull-down device threshold voltage by at least about 40 mV.

17. An integrated circuit, including:
a first SRAM array in a semiconductor substrate, wherein the first SRAM array includes a plurality of two-port SRAM cells, wherein each two-port SRAM cell includes a write port portion and a read port portion,
wherein the write port portion includes:
first and second pull-up devices;
first and second pull-down devices configured with the first and second pull-up devices to form first and second cross-coupled inverters for data storage;

wherein the read port portion includes a read pull-down device coupled to the first inverter;

a second SRAM array in the semiconductor substrate, wherein the second SRAM array includes a plurality of single-port SRAM cells, wherein each single-port SR

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title

• H01L27/1104 Primary

  Electricity · mapped topic