Image sensor

Patent metadata

Field	Value
Publication number	US-12199127-B2
Application number	US-202117528237-A
Country	US
Kind code	B2
Filing date	Nov 17, 2021
Priority date	Mar 16, 2021
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

First claim

What is claimed is:

1. An image sensor comprising:
a first substrate;
a photoelectric conversion region in the first substrate;
a first interlayer insulating layer on the first substrate and positioned above the photoelectric conversion region;
a transistor that includes a bonding insulating layer on the first interlayer insulating layer and positioned above the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer;
a bias pad that is spaced apart from the semiconductor layer by the bonding insulating layer, the bias pad overlaps the first gate in a planar view; and
a second interlayer insulating layer covering the transistor.

2. The image sensor of claim 1 , wherein the bias pad is configured to receive a voltage.

3. The image sensor of claim 2 , wherein the bias pad is configured to adjust a threshold voltage of the transistor.

4. The image sensor of claim 1 , wherein the transistor includes a fully depleted silicon on insulator (FD SOI) transistor or a partially depleted silicon on insulator (PD SOI) transistor.

5. The image sensor of claim 1 , further comprising a bias via penetrating the first interlayer insulating layer and directly contacting the bias pad.

6. The image sensor of claim 1 , wherein a top surface of the bias pad is coplanar with a top surface of the first interlayer insulating layer.

7. The image sensor of claim 1 , further comprising:
a first intervening layer between the first interlayer insulating layer and the bonding insulating layer; and
a second intervening layer between the semiconductor layer and the bonding insulating layer.

8. The image sensor of claim 1 , further comprising:
a connection pad between the first interlayer insulating layer and the bonding insulating layer; and
a connection via penetrating the second interlayer insulating layer and the bonding insulating layer and directly contacting the connection pad.

9. The image sensor of claim 8 , further comprising a second gate on the first substrate, wherein the connection pad is connected to the second gate.

10. The image sensor of claim 8 , further comprising an impurity region in the first substrate, wherein the connection pad is connected to the impurity region.

11. The image sensor of claim 8 , wherein a top surface of the connection pad is coplanar with a top surface of the first interlayer insulating layer.

12. The image sensor of claim 8 , further comprising:
a first bonding pad directly connected to the connection via and positioned on the second interlayer insulating layer; and
a logic structure on the second interlayer insulating layer and the first bonding pad,
wherein the logic structure comprises:
a second substrate;
a logic circuit on the second substrate;
a third interlayer insulating layer covering the second substrate and the logic circuit; and
a second bonding pad positioned on the third interlayer insulating layer, connected to the logic circuit, and directly contacting the first bonding pad.

13. An image sensor comprising:
a substrate;
a photoelectric conversion region in the substrate;
a transfer gate on the substrate;
a first interlayer insulating layer covering the substrate and the transfer gate;
a first connection pad positioned on the first interlayer insulating layer and connected to the transfer gate;
a bias pad positioned on the first interlayer insulating layer;
a bonding insulating layer on the first interlayer insulating layer, the first connection pad, and the bias pad;
a semiconductor layer on the bonding insulating layer;
a selection gate positioned on the semiconductor layer and overlapping the bias pad in a planar view;
a second interlayer insulating layer covering the selection gate; and
a first connection via penetrating the second interlayer insulating layer and the bonding insulating layer and directly contacting the first connection pad.

14. The image sensor of claim 13 , further comprising:
a floating diffusion region in the substrate;
a second connection pad positioned between the first interlayer insulating layer and the bonding insulating layer and connected to the floating diffusion region; and
a second connection via penetrating the second interlayer insulating layer and the bonding insulating layer and directly contacting the second connection pad.

15. The image sensor of claim 13 , further comprising:
a source follower gate on the substrate;
a third connection pad positioned between the first interlayer insulating layer and the bonding insulating layer and connected to the source follower gate; and
a third connection via penetrating the second interlayer insulating layer and the bonding insulating layer and directly contacting the third connection pad.

16. The image sensor of claim 13 , further comprising:
a reset gate on the substrate;
a fourth connection pad positioned between the first interlayer insulating layer and the bonding insulating layer and connected to the reset gate; and
a fourth connection via penetrating the second interlayer insulating layer and the bonding insulating layer and directly contacting the fourth connection pad.

17. The image sensor of claim 13 , further comprising a reset gate on the semiconductor layer.

18. The image sensor of claim 13 , wherein a thickness of the semiconductor layer is in a range of about 1 nm to about 10 nm.

19. The image sensor of claim 13 , wherein a top surface of the first connection pad, a top surface of the bias pad, and a top surface of the first interlayer insulating layer are coplanar with each other.

20. An image sensor comprising:
a pixel structure; and
a logic structure on the pixel structure, wherein
the pixel structure comprises:
a first substrate;
a photoelectric conversion region in the first substrate;
a first interlayer insulating layer on the first substrate;
a bonding insulating layer on the first interlayer insulating layer;
a semiconductor layer on the bonding insulating layer;
a gate on the semiconductor layer;
a bias pad that is spaced apart from the semiconductor layer by the bonding insulating layer and overlaps the gate in a planar view;
a second interlayer insulating layer covering the gate;
a first bonding pad positioned on the second interlayer insulating layer and connected to the gate, wherein
the logic structure comprises:
a second substrate;
a logic circuit on the second substrate;
a third interlayer insulating layer covering the second substrate and the logic circuit; and
a second bonding pad positioned on the third interlayer insulating layer and connected to the logic circuit, wherein
the first bonding pad directly contacts the second bonding pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Jeongsoon
• Ryu Mintae
• Lee Minsu
• Lee Wonsok

Classifications

• H10F39/809

  of hybrid image sensors · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/805

  Coatings · CPC title

• H10F39/811 Primary

  Interconnections · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title