CMOS image sensor chips with stacked scheme and methods for forming the same

Patent metadata

Field	Value
Publication number	US-10090349-B2
Application number	US-201213571099-A
Country	US
Kind code	B2
Filing date	Aug 9, 2012
Priority date	Aug 9, 2012
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A device includes an image sensor chip having an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip, wherein the read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip, wherein the peripheral circuit chip includes a logic circuit.

First claim

What is claimed is:

1. A device comprising:
an image sensor chip comprising:
a semiconductor substrate and an image sensor; and
an interconnect structure underlying the semiconductor substrate, wherein the interconnect structure comprises dielectric layers and metal lines and vias in the dielectric layers, wherein the interconnect structure comprises:
a first portion overlapped by the semiconductor substrate; and
a second portion laterally extending beyond the semiconductor substrate; and

a read-out chip underlying and bonded to the image sensor chip, wherein the read-out chip comprises a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein, and wherein the logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit;
a peripheral circuit chip underlying and bonded to the read-out chip, wherein the peripheral circuit chip comprises a logic circuit; and
an electrical connector comprising a bottom surface contacting a top surface of a top dielectric layer, wherein the top dielectric layer is in the second portion of the interconnect structure, wherein the semiconductor substrate has a portion level with the electrical connector.

2. The device of claim 1 , wherein the image sensor chip further comprises:
a via electrically coupled to the electrical connector, wherein the via extends into the second portion of the interconnect structure of the image sensor chip.

3. The device of claim 1 , wherein the image sensor chip further comprises:
a transfer gate transistor therein, wherein the transfer gate transistor is electrically coupled to the image sensor, and wherein the transfer gate transistor is a part of the same pixel unit; and
a bond pad at a bottom surface of the image sensor chip, wherein the bond pad is electrically connected to a gate of the transfer gate transistor, and the bond pad has a bottom surface coplanar with the bottom surface of the image sensor chip.

4. The device of claim 3 , wherein the image sensor chip is substantially free from additional transistors other than transfer gate transistors, with the transfer gate transistors being comprised in pixel units.

5. The device of claim 1 , wherein the image sensor chip further comprises a floating diffusion capacitor therein, wherein the floating diffusion capacitor is electrically coupled to the image sensor, and wherein the floating diffusion capacitor is a part of the same pixel unit.

6. The device of claim 1 , wherein the read-out chip comprises the reset transistor, the source follower, and the row selector.

7. The device of claim 1 , wherein the logic circuit in the peripheral circuit chip further comprises an Image Signal Processing (ISP) circuit in the read-out chip, wherein the ISP circuit comprises a circuit selected from the group consisting essentially of an Analog-to-Digital Converter (ADC), a Correlated Double Sampling (CDS) circuit, a row decoder, and combinations thereof.

8. The device of claim 1 , wherein the electrical connector has a bottom surface substantially coplanar with a bottom surface of the semiconductor substrate.

9. A device comprising:
an image sensor chip comprising:
a semiconductor substrate;
a sensor array comprising a plurality of image sensors in the semiconductor substrate;
a plurality of transfer gate transistors, wherein each of the plurality of transfer gate transistors is electrically coupled to one of the plurality of image sensors;
a first plurality of bond pads, each connected to a gate of one of the plurality of transfer gate transistors; and
a wire bond pad configured to form wire bonding thereon, wherein the wire bond pad overlaps a portion of the image sensor chip, and the portion of the image sensor chip is level with a bottom portion of the semiconductor substrate;

a read-out chip underlying and bonded to the image sensor chip, wherein the read-out chip comprises:
a second plurality of bond pads, each bonded to and in physical contact with one of the first plurality of bond pads;
a plurality of reset transistors;
a plurality of source followers; and
a plurality of row selectors electrically coupled to the plurality of image sensors and the plurality of transfer gate transistors to form a pixel unit array comprising a plurality of pixel units; and

a peripheral circuit chip underlying and bonded to the read-out chip, wherein the peripheral circuit chip comprises a circuit selected from the group consisting essentially of an Analog-to-Digital Converter (ADC), a Correlated Double Sampling (CDS) circuit, a row decoder, and combinations thereof.

10. The device of claim 9 , wherein the image sensor chip and the read-out chip are bonded through a hybrid bonding comprising a metal-to-metal bonding and an oxide-to-oxide bonding.

11. The device of claim 9 , wherein the image sensor chip further comprises:
a plurality of floating diffusion capacitors, and wherein each of the plurality of floating diffusion capacitors is electrically coupled to one of the plurality of image sensors, and forms a part of a respective one of the plurality of pixel units; and
a third plurality of bond pads, each connected to one of the plurality of floating diffusion capacitors.

12. The device of claim 9 , wherein the semiconductor substrate comprises a portion higher than a tops surface of the wire bond pad.

13. A method comprising:
performing a first bonding step to bond an image sensor chip to, and underlying, a read-out chip, wherein the image sensor chip comprises:
a first semiconductor substrate; and
an image sensor disposed adjacent to a surface of the first semiconductor substrate;

wherein the read-out chip comprises:
a second semiconductor substrate; and
a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof at a surface of the second semiconductor substrate, wherein the logic device and the image sensor are electrically coupled to each other, and form parts of a same pixel unit;

performing a second bonding step to bond a peripheral circuit chip to, and underlying, the read-out chip, wherein the peripheral circuit chip comprises:
a third semiconductor substrate; and
a logic circuit at a surface of the third semiconductor substrate; and

etching-through a portion of the first semiconductor substrate to expose a dielectric layer in the image sensor chip, wherein the dielectric layer is underlying the first semiconductor substrate; and
forming a wire bond pad in a space left by the etched portion of the first semiconductor substrate.

14. The method of claim 13 , wherein the first and the second bonding steps are performed at wafer level, with the image sensor chip, the read-out chip, and the peripheral circuit chip being in respective un-sawed wafers.

15. The method of claim 13 further comprising, after the second bonding step, forming color filters and micro-lenses at a top surface of the image sensor chip.

16. The method of claim 13 , wherein the first semiconductor substrate comprises a center portion, and edge portions on opposite sides of the center portion, with the edge portions extending to edges of the image sensor chip, and during the etching-through, the edge portions are removed.

17. The method of claim 13 , wherein substantially no Image Signal Processing (ISP) circuit is in the image sensor chip and the read-out chip.

18. The method of claim 13 , wherein the forming the wire b

Assignees

• Wan Meng Hsun
• Chen Szu Ying
• Yaung Dun Nian
• Liu Jen Cheng
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wan Meng-Hsun
• Chen Szu-Ying
• Yaung Dun-Nian
• Liu Jen-Cheng

Classifications

• H01L27/1464

  Electricity · mapped topic

• H01L27/1469

  Electricity · mapped topic

• H01L27/14634 Primary

  Electricity · mapped topic

• H10F39/199

  Back-illuminated image sensors · CPC title

• H10F39/018

  of hybrid image sensors · CPC title