Capacitance device in a stacked scheme and methods of forming the same

Patent metadata

Field	Value
Publication number	US-9613994-B2
Application number	US-201414333307-A
Country	US
Kind code	B2
Filing date	Jul 16, 2014
Priority date	Jul 16, 2014
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

Embodiments of the present disclosure include devices and sensor packages and methods of forming the same. An embodiment is a device including a first semiconductor chip. The first semiconductor chip includes a first substrate, a first conductive pad over the first substrate. The device further includes a second semiconductor chip having a second surface bonded to a first surface of the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive pad over the second substrate. The second conductive pad and the first conductive pad form a first capacitor.

First claim

What is claimed is:

1. A device comprising:
a first semiconductor chip comprising:
a first substrate; and
a first conductive pad over the first substrate; and

a second semiconductor chip having a second surface bonded to a first surface of the first semiconductor chip, the first surface physically contacting the second surface, the second semiconductor chip comprising:
a second substrate; and
a second conductive pad over the second substrate, the second conductive pad and the first conductive pad forming a first capacitor.

2. The device of claim 1 , wherein the first capacitor is a bridge capacitor between the first semiconductor chip and the second semiconductor chip.

3. The device of claim 1 , wherein the first semiconductor chip is a sensor chip comprising a photodiode therein, and wherein the second semiconductor chip is an application specific integrated circuit (ASIC) chip comprising a logic device therein.

4. The device of claim 3 , wherein the logic device comprises a first reset transistor, a source follower, and a row selector.

5. The device of claim 3 , wherein the ASIC chip further comprises an image signal processing circuit, the image signal processing circuit comprising a circuit selected from the group consisting essentially of an analog-to-digital converter (ADC), a correlated double sampling (CDS) circuit, a row decoder, and combinations thereof.

6. The device of claim 3 , wherein the photodiode and the logic device are coupled to each other through the first capacitor forming a pixel unit.

7. The device of claim 6 , wherein the sensor chip further comprises a transfer gate transistor coupled to the photodiode and a second reset transistor coupled to the transfer gate transistor and the first capacitor, the transfer gate transistor and the second reset transistor being a part of the pixel unit.

8. The device of claim 1 , wherein the first semiconductor chip has a first power supply voltage, and wherein the second semiconductor chip has a second power supply voltage, the second power supply voltage being lower than the first power supply voltage.

9. The device of claim 1 , wherein the first conductive pad and the second conductive pad of the first capacitor are separated by a dielectric layer, the dielectric layer being a bonding interface between the first semiconductor chip and the second semiconductor chip.

10. A device comprising:
a sensor chip comprising a plurality of pixels disposed in a first side of a first substrate and a first plurality of conductive pads over the first side of the first substrate, each of the first plurality of conductive pads being coupled to one of the plurality of pixels; and
a circuit chip underlying and bonded to the sensor chip, the circuit chip comprising a plurality of active devices disposed in a second substrate and a second plurality of conductive pads over the second substrate, each of the second plurality of conductive pads being coupled to at least one of plurality of active devices, each of the second plurality of conductive pads being paired with one of the first plurality of conductive pads forming a plurality of capacitors.

11. The device of claim 10 , wherein the sensor chip further comprises a plurality of transfer gates coupled to the plurality of pixels and a first plurality of reset transistors coupled to the plurality of transfer gates and the first plurality of conductive pads of the plurality of capacitors.

12. The device of claim 11 , wherein the active devices of the circuit chip comprise a second plurality of reset transistors, a plurality of source followers, and a plurality of row selectors.

13. The device of claim 10 , wherein the sensor chip has a first power supply voltage and the circuit chip has a second power supply voltage, the first power supply voltage being higher than the second power supply voltage.

14. The device of claim 10 , wherein the sensor chip further comprises a first redistribution layer between the first side of the first substrate and the first plurality of conductive pads, the first redistribution layer comprising a plurality of dielectric layers with conductive elements formed therein, the conductive elements of the first redistribution layer coupling the plurality of pixels to the first plurality of conductive pads, and wherein the circuit chip further comprises a second redistribution layer between the second substrate and the second plurality of conductive pads, the second redistribution layer comprising a plurality of dielectric layers with conductive elements formed therein, the conductive elements of the second redistribution layer coupling the plurality of active devices to the second plurality of conductive pads.

15. The device of claim 14 further comprising a first bond pad over a portion of the second redistribution layer, the first bond pad coupled to a first via extending through a portion of the second redistribution layer and coupled to at least one of the conductive elements of the second redistribution layer, the first bond pad configured to receive and conduct a direct current (DC) signal to the circuit chip.

16. The device of claim 15 further comprising a second bond pad over a portion of the first redistribution layer, the second bond pad coupled to a second via extending through a portion of the first redistribution layer and coupled to at least one of the conductive elements of the first redistribution layer, the second bond pad configured receive and conduct DC signal to the sensor chip.

17. The device of claim 16 , wherein the first bond pad and the second bond pad are at a same level.

18. A method comprising:
forming a first semiconductor chip comprising forming a first conductive pad over a first substrate;
forming a second semiconductor chip comprising forming a second conductive pad over a second substrate;
bonding a first surface of the first semiconductor chip to a second surface of the second semiconductor chip using a direct bonding method; and
forming a first capacitor with the first conductive pad and the second conductive pad being electrodes of the first capacitor.

19. The method of claim 18 , wherein the first semiconductor chip is a sensor chip and wherein the forming the first semiconductor chip further comprises forming a photodiode in the first substrate, and wherein the second semiconductor chip is an application specific integrated circuit (ASIC) chip and wherein the forming the second semiconductor chip further comprises forming a logic device in the second substrate.

20. The method of claim 18 , wherein the forming the first semiconductor chip further comprises forming a first dielectric layer over the first conductive pad, the first dielectric layer forming the first surface of the first semiconductor chip, wherein the forming the second semiconductor chip comprises forming a second dielectric layer over the second conductive pad, the second dielectric layer forming the second surface of the second semiconductor chip, the first and second dielectric layers forming an insulator for the first capacitor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yamashita Yuichiro

Classifications

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H01L27/14612

  Electricity · mapped topic

• H01L27/14689

  Electricity · mapped topic

• H01L27/1469

  Electricity · mapped topic