Band-pass filter for stacked sensor

Patent metadata

Field	Value
Publication number	US-10651225-B2
Application number	US-201816163908-A
Country	US
Kind code	B2
Filing date	Oct 18, 2018
Priority date	Sep 27, 2018
Publication date	May 12, 2020
Grant date	May 12, 2020

Abstract

In some embodiments, the present disclosure relates to a three-dimensional integrated chip. The three-dimensional integrated chip includes a first integrated chip (IC) die and a second IC die. The first IC die has a first image sensor element configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second IC die has a second image sensor element configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. A first band-pass filter is arranged between the first IC die and the second IC die and is configured to reflect electromagnetic radiation that is within the first range of wavelengths.

First claim

What is claimed is:

1. A three-dimensional integrated chip, comprising:
a first integrated chip (IC) die having a first image sensor element configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths;
a second IC die having a second image sensor element configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths;
a first band-pass filter arranged between the first IC die and the second IC die and configured to reflect electromagnetic radiation that is within the first range of wavelengths; and
a waveguide arranged over the first IC die, the waveguide having a bottom surface facing the first IC die and a top surface facing away from the first IC die, the bottom surface having a smaller width than the top surface.

2. The integrated chip of claim 1 , further comprising:
a second band-pass filter separated from the first IC die by the second IC die, wherein the second band-pass filter is configured to reflect electromagnetic radiation that is within the second range of wavelengths.

3. The integrated chip of claim 1 , wherein the first band-pass filter comprises:
a first layer of material having a first refractive index; and
a second layer of material having a second refractive index that is less than the first refractive index.

4. The integrated chip of claim 1 , wherein the first band-pass filter comprises:
a first layer of silicon;
a first layer of silicon dioxide; and
a second layer of silicon, wherein the first layer of silicon dioxide continuously extends from a first surface contacting the first layer of silicon to a second surface contacting the second layer of silicon.

5. The integrated chip of claim 1 , wherein the first IC die comprises:
a first substrate; and
a first dielectric structure comprising a plurality of stacked inter-level dielectric (ILD) layers surrounding a plurality of conductive interconnect layers.

6. The integrated chip of claim 5 , wherein the first band-pass filter is arranged between the first dielectric structure and the second IC die.

7. The integrated chip of claim 6 , further comprising:
a dielectric waveguide arranged laterally between sidewalls of the first dielectric structure and vertically extending through the plurality of stacked ILD layers at a position overlying the first band-pass filter.

8. The integrated chip of claim 5 , wherein the first band-pass filter is arranged between sidewalls of the first dielectric structure.

9. The integrated chip of claim 1 , wherein the first band-pass filter is configured to pass electromagnetic radiation within a passband including the second range of wavelengths.

10. The integrated chip of claim 1 ,
wherein the first IC die comprises a first substrate having a substantially planar first upper surface facing away from the second IC die; and
wherein the second IC die comprises a second substrate having a second upper surface facing the first IC die, wherein the second upper surface comprises angled sidewalls defining one or more recesses within the second upper surface.

11. A stacked image sensor device, comprising:
a first image sensor element disposed within a first substrate and configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths, wherein the first substrate has a first surface configured to receive incident radiation and a second surface opposing the first surface;
a second image sensor element disposed within a second substrate and configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths; and
a first band-pass filter arranged between the second surface of the first substrate and the second substrate and comprising alternating layers of a first material having a first refractive index and a second material having a second refractive index that is different than the first refractive index, wherein the first band-pass filter is configured to pass electromagnetic radiation within the second range of wavelengths and to reflect electromagnetic radiation within the first range of wavelengths;
a first dielectric structure arranged along the second surface of the first substrate and comprising a first plurality of stacked inter-level dielectric (ILD) layers surrounding a first plurality of conductive interconnect layers;
a second dielectric structure arranged along a surface of the second substrate and comprising a second plurality of stacked ILD layers surrounding a second plurality of conductive interconnect layers; and
a through-substrate-via (TSV) extending through the second substrate and electrically coupling the first plurality of conductive interconnect layers to the second plurality of conductive interconnect layers, wherein the TSV extends through the first band-pass filter.

12. The stacked image sensor device of claim 11 , further comprising:
a second band-pass filter separated from the first substrate by the second substrate, wherein the second band-pass filter comprises alternating layers of a third material having a third refractive index and a fourth material having a fourth refractive index that is less than the third refractive index.

13. The stacked image sensor device of claim 12 , wherein the first band-pass filter has a different number of layers than the second band-pass filter.

14. The stacked image sensor device of claim 12 , further comprising:
a third substrate separated from the second substrate by the second band-pass filter; and
a third image sensor element disposed within the third substrate and configured to generate electrical signals from electromagnetic radiation within a third range of wavelengths that is different than the first range of wavelengths and the second range of wavelengths.

15. The stacked image sensor device of claim 11 , wherein the first band-pass filter is arranged between sidewalls of the first dielectric structure.

16. The stacked image sensor device of claim 11 , wherein the first substrate has a first thickness and the second substrate has a second thickness that is greater than the first thickness.

17. A three-dimensional integrated chip, comprising:
a first integrated chip (IC) die having a first image sensor element configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths;
a second IC die having a second image sensor element configured to generate electrical signals from electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths; and
a first band-pass filter arranged between the first IC die and the second IC die and configured to reflect electromagnetic radiation that is within the first range of wavelengths, wherein the first band-pass filter comprises:
a first layer of silicon;
a first layer of silicon dioxide; and
a second layer of silicon, wherein the first layer of silicon dioxide continuously extends from a first surface contacting the first layer of silicon to a second surface contacting the second layer of silicon.

18. The integrated chip of claim 1 , wherein the waveguide is a dielectric material.

19. The integrated chip of claim 1 , further comprising:
a dielectric layer arranged over the first IC die and laterally surrounding the waveguide, wherein the waveguide has a first index of refraction that is different than a second index of r

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Cheng Yu
• Chuang Chun-Hao
• Tseng Chien-Hsien
• Hashimoto Kazuaki
• Chou Keng-Yu
• Chiang Wei-Chieh
• Wu Wen-Hau

Classifications

• H01L27/14629

  Electricity · mapped topic

• H01L27/14643 Primary

  Electricity · mapped topic

• H01L23/64

  Electricity · mapped topic

• H01L27/14621

  Electricity · mapped topic

• H01L23/552

  Electricity · mapped topic