Stacked image sensor capacitors and related methods

Patent metadata

Field	Value
Publication number	US-10403659-B2
Application number	US-201816116634-A
Country	US
Kind code	B2
Filing date	Aug 29, 2018
Priority date	Aug 1, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Implementations of image sensors may include a first die including an image sensor array and a first plurality of interconnects where the image sensor array includes a plurality of photodiodes and a plurality of transfer gates. The image sensor array may also include a second die including a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors. The first die may be coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects. No more than eight photodiodes of the plurality of photodiodes of the first die may be electrically coupled with no more than four capacitors of the plurality of capacitors.

First claim

What is claimed is:

1. An image sensor comprising:
a first die comprising an image sensor array and a first plurality of interconnects; and
a second die comprising a second plurality of interconnects and a plurality of capacitors, each capacitor selected from the group consisting of deep trench capacitors, metal-insulator-metal (MIM) capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and 3D stacked capacitors;
wherein the first die is coupled to the second die through the first plurality of interconnects and through the second plurality of interconnects; and
wherein each capacitor comprises a total capacitance of at least 100 fF.

2. The image sensor of claim 1 , wherein the image sensor array comprises a plurality of photodiodes, wherein each photodiode of the plurality of photodiodes is electrically coupled to only one capacitor of the plurality of capacitors.

3. The image sensor of claim 1 , further comprising a plurality of transfer gates.

4. The image sensor of claim 1 , wherein each capacitor has a density of at least 25 fF/μm 2 .

5. An image sensor comprising:
a photodiode die comprising an image sensor array;
a pixel device die comprising a first side and a second side, the first side bonded to the photodiode die, the pixel device die comprising a plurality of capacitors selected from the group consisting of deep trench capacitors, MIM capacitors, PIP capacitors, and 3D stacked capacitors; and
a digital signal processor (DSP) die bonded to the second side of the pixel device die;
wherein a through silicon via (TSV) electrically couples the pixel device die with the DSP die.

6. The image sensor of claim 5 , wherein the image sensor array comprises a plurality of photodiodes, wherein each photodiode of the plurality of photodiodes die is electrically coupled to only one capacitor of the plurality of capacitors.

7. The image sensor of claim 5 , each capacitor comprising a total capacitance of at least 100 fF.

8. The image sensor of claim 5 , wherein the plurality of capacitors are deep trench capacitors and each photodiode is electrically coupled to a first deep trench capacitor for a signal value and a second deep trench capacitor for a reference value.

9. The image sensor of claim 5 , wherein the plurality of capacitors are deep trench capacitors and the pixel device die further comprises a base oxide layer contacting a terminal end of each deep trench capacitor.

10. The image sensor of claim 5 , wherein the plurality of capacitors are deep trench capacitors and at least a portion of the TSV is wider than each deep trench capacitor.

11. The image sensor of claim 5 , wherein each capacitor has a density of at least 25 fF/μm 2 .

12. The image sensor of claim 5 , wherein the photodiode die is hybrid bonded to the pixel device die and the pixel device die is fusion bonded to the DSP die.

13. The image sensor of claim 5 , wherein the photodiode die is hybrid bonded to the pixel device die and the pixel device die is hybrid bonded to the DSP die.

14. An image sensor comprising:
a photodiode die comprising an image sensor array comprising a plurality of photodiodes;
a pixel device die comprising a first side and a second side, the first side bonded to the photodiode die, the pixel device die comprising a plurality of deep trench capacitors; and
a digital signal processor (DSP) die bonded to the second side of the pixel device die;
wherein a through silicon via (TSV) electrically couples the pixel device die with the DSP die.

15. The image sensor of claim 14 , wherein the pixel device die further comprises a base oxide layer contacting a terminal end of each deep trench capacitor.

16. The image sensor of claim 14 , wherein at least a portion of the TSV is wider than each deep trench capacitor.

17. The image sensor of claim 14 , wherein each capacitor has a density of at least 25 fF/μm 2 .

18. The image sensor of claim 14 , wherein the TSV is a polysilicon filled TSV.

19. The image sensor of claim 14 , wherein the TSV narrows from the pixel device die to the DSP die.

20. The image sensor of claim 14 , wherein the TSV widens from the pixel device die to the DSP die.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Gambino Jeffrey Peter
• Rodriguez Angel
• Price David T
• Neuls Jeffery Allen
• Bates Kenneth Andrew
• Mauritzson Rick

Classifications

• H01L27/1463

  Electricity · mapped topic

• H01L27/0617

  Electricity · mapped topic

• H01L27/14634

  Electricity · mapped topic

• H01L27/14609 Primary

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic