Semiconductor device having interconnection lines with different linewidths and metal patterns

Patent metadata

Field	Value
Publication number	US-12199042-B2
Application number	US-202217590238-A
Country	US
Kind code	B2
Filing date	Feb 1, 2022
Priority date	Dec 16, 2019
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

A semiconductor device includes transistors on a substrate, a first interlayered insulating layer on the transistors, first and second lower interconnection lines in an upper portion of the first interlayered insulating layer, and first and second vias on the first and second lower interconnection lines, respectively. Each of the first and second lower interconnection lines includes a first metal pattern. The first lower interconnection line further includes a second metal pattern, on the first metal pattern with a metallic material different from the first metal pattern. The second metal pattern is absent in the second lower interconnection line. The second via includes first and second portions, which are in contact with respective top surfaces of the first interlayered insulating layer and the second lower interconnection line, and the lowest level of a bottom surface of the second portion is lower than that of a bottom surface of the first via.

First claim

What is claimed is:

1. A semiconductor device, comprising
transistors on a substrate;
an interlayered insulating layer on the transistors; and
a first interconnection line, a second interconnection line, and a third interconnection line that are in an upper portion of the interlayered insulating layer,
wherein a linewidth of the first interconnection line is larger than a linewidth of the second interconnection line,
a linewidth of the third interconnection line is smaller than a linewidth of the second interconnection line,
each of the first and second interconnection lines includes a first metal pattern and a second metal pattern on the first metal pattern, the second metal pattern containing a metallic material different from the first metal pattern,
a volume ratio of the first metal pattern in the first interconnection line to a total volume of the first interconnection line is smaller than a volume ratio of the first metal pattern in the second interconnection line to a total volume of the second interconnection line,
a volume ratio of the second metal pattern in the first interconnection line to the total volume of the first interconnection line is greater than a volume ratio of the second metal pattern in the second interconnection line to the total volume of the second interconnection line, and
the third interconnection line includes the first metal pattern and exclude the second metal pattern.

2. The semiconductor device of claim 1 , wherein the first metal pattern comprises a metallic material whose electron mean free path (eMFP) is smaller than 12 nm, and
the second metal pattern comprises a metallic material whose eMFP is larger than 12 nm.

3. The semiconductor device of claim 2 , wherein the first metal pattern comprises ruthenium (Ru), cobalt (Co), tungsten (W), or molybdenum (Mo), and
the second metal pattern comprises copper (Cu).

4. The semiconductor device of claim 1 , wherein each of the first and second interconnection lines further includes a barrier metal pattern between the interlayered insulating layer and the first metal pattern, and
an upper portion of the barrier metal pattern is recessed to define a recess region between the interlayered insulating layer and the first metal pattern.

5. The semiconductor device of claim 1 , wherein each of the first and second interconnection lines further includes a metal capping pattern covering a top surface of the first metal pattern and a top surface of the second metal pattern, and
the metal capping pattern comprises ruthenium (Ru), cobalt (Co), or graphene.

6. The semiconductor device of claim 1 , wherein each of the first and second interconnection lines further includes a via portion as a lower portion thereof, and
the second metal pattern is absent in the via portion.

7. The semiconductor device of claim 1 , wherein the first metal pattern of each of the first and second interconnection lines includes a lower portion and a pair of upper portions vertically extended from the lower portion, and
the second metal pattern is in a space enclosed by the lower portion and the pair of upper portions.

8. The semiconductor device of claim 1 , wherein a highest level of a top surface of the third interconnection line is lower than a highest level of a top surface of the first interconnection line.

9. The semiconductor device of claim 1 , wherein the second metal pattern has a largest volume in the first interconnection line, and
the first metal pattern has a largest volume in the third interconnection line.

10. A semiconductor device, comprising
transistors on a substrate;
an interlayered insulating layer on the transistors; and
an interconnection line in an upper portion of the interlayered insulating layer,
wherein the interconnection line includes a barrier metal pattern, a first metal pattern on the barrier metal pattern and a second metal pattern on the first metal pattern, the second metal pattern having a first uppermost surface level, the first metal pattern having a second uppermost surface level lower than the first uppermost surface level, and the barrier metal pattern having a third uppermost surface level lower than the second uppermost surface level,
the second metal pattern contains a metallic material different from the first metal pattern,
the interconnection line further includes a via portion in a lower portion of the interlayered insulating layer, the via portion vertically extending toward a lower metal layer,
the via portion includes the barrier metal pattern and the first metal pattern and excludes the second metal pattern.

11. The semiconductor device of claim 10 , wherein a thickness of an upper portion of the first metal pattern of the interconnection line in a horizontal direction is a first thickness,
a thickness of the first metal pattern of the via portion in the horizontal direction is a second thickness, and
the second thickness is larger than two times the first thickness.

12. The semiconductor device of claim 10 , wherein the barrier metal pattern is between the interlayered insulating layer and the first metal pattern.

13. The semiconductor device of claim 10 , wherein the first metal pattern includes a lower portion and a pair of upper portions vertically extended from the lower portion,
the second metal pattern is in a space enclosed by the lower portion and the pair of upper portions, and
the via portion is extended from the lower portion.

14. The semiconductor device of claim 10 , wherein the first metal pattern comprises a metallic material whose electron mean free path (eMFP) is smaller than 12 nm, and
the second metal pattern comprises a metallic material whose eMFP is larger than 12 nm.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Wonhyuk
• Lee Jongjin
• Kim Rakhwan
• Jung Eun-Ji

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title