Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9721894-B2
Application number	US-201615361699-A
Country	US
Kind code	B2
Filing date	Nov 28, 2016
Priority date	Sep 28, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a dielectric layer over a substrate;
forming an opening in the dielectric layer, the opening having a first region, a second region and a third region, a width of the first region being greater than a width of the second region, the third region being disposed over and connecting the first and second regions;
forming a first metal layer in the first to third regions;
forming a second metal layer in the first and third regions; and
performing a planarization operation on the first and second metal layers so that a first metal wiring by the first region, a second metal wiring by the second region and a third metal wiring by the third region connecting the first and second metal wirings are formed, wherein:
a metal material of the first metal layer is different from a metal material of the second metal layer, and
the first and third metal wirings include the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

2. The method of claim 1 , further comprising, before forming the first metal layer, forming a third metal layer in the opening and over an upper surface of the dielectric layer.

3. The method of claim 1 , wherein:
the metal material of the first metal layer includes one of Co, Ru, Al and Ag, and
the metal material of the second metal layer includes one of Cu, Co, Al and Ag.

4. The method of claim 1 , wherein:
the metal material of the first metal layer includes Co, and
the metal material of the second metal layer includes Cu.

5. The method of claim 2 , wherein the third metal layer includes one of TiN and TaN.

6. The method of claim 2 , wherein the planarization operation includes:
a first planarization operation, in which an etching rate for the second metal layer is higher than an etching rate for the first metal layer, and
a second planarization operation performed after the first planarization operation, in which the etching rate for the second metal layer is smaller than the etching rate for the first metal layer.

7. The method of claim 6 , wherein the second planarization operation uses the third metal layer disposed over the upper surface of the dielectric layer as an etching stopper.

8. The method of claim 6 , wherein the first planarization operation is performed such that the first metal layer is not exposed.

9. The method of claim 7 , wherein the planarization operation includes:
a third planarization operation performed after the second planarization operation,
wherein the third metal layer disposed over the upper surface of the dielectric layer is removed by the third planarization operation.

10. The method of claim 1 , wherein the first region and the second region are recesses laterally extending as line patterns in a plan view.

11. The method of claim 1 , wherein the first region and the second region are holes vertically extending in the dielectric layer.

12. The method of claim 1 , further comprising performing a heat treatment after the forming the first metal layer and before the forming the second metal layer.

13. The method of claim 1 , further comprising performing a heat treatment after the forming the second metal layer.

14. A semiconductor device, comprising:
a metal wiring disposed an interlayer dielectric layer disposed over a substrate, the wiring pattern having a first region, a second region and a third region, a width of the first region being greater than a width of the second region, the third region being disposed on and connecting the first and second regions, wherein:
the first region of the metal wiring includes at least a first metal layer made of a first material and a second metal layer made of a second metal material disposed over the first metal layer,
the second region of the metal wiring includes a first metal layer made of the first metal material but does not include any metal layer made of the second metal material,
the third region of the metal wiring includes at least a first metal layer made of the first material and a second metal layer made of the second metal material disposed over the first metal layer, and
the first metal material is different from the second metal material.

15. The semiconductor device of claim 14 , wherein:
the first region of the metal wiring further includes a barrier metal layer made of a third metal material disposed under the first metal layer of the first region, and
the second region of the metal wiring further includes a barrier metal layer made of the third metal material disposed under the first metal layer of the second region.

16. The semiconductor device of claim 14 , wherein:
the first metal material includes one of Cu, Co, Ru, Al and Ag, and
the second metal material includes one of Cu, Co, Al and Ag.

17. The semiconductor device of claim 14 , wherein:
the metal material of the first metal layer includes Co, and
the metal material of the second metal layer includes Cu.

18. The semiconductor device of claim 15 , wherein the third metal material includes one of TiN and TaN.

19. A semiconductor device, comprising:
a metal wiring disposed an interlayer dielectric layer disposed over a substrate, the wiring pattern having a first region, a second region and a third region, a width of the first region being greater than a width of the second region, the third region being disposed on and connecting the first and second regions, wherein:
the first and third regions of the metal wiring include a layered structure having more than one conductive layer,
the second region of the metal wiring includes a layered structure having one or more conductive layers,
the layered structure of the first and second region of the metal wiring is different from the layered structure of the second region of the metal wiring.

20. The semiconductor device of claim 18 , wherein:
a number of conductive layers in the first region is greater than a number of conductive layers in the second region.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fu Shih-Kang
• Wu Hsien-Chang
• Su Li-Lin
• Lee Ming-Han
• Shue Shau-Lin

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/264

  by chemical means · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title