Semiconductor device having a metal via

Patent metadata

Field	Value
Publication number	US-2018358293-A1
Application number	US-201815868379-A
Country	US
Kind code	A1
Filing date	Jan 11, 2018
Priority date	Jun 8, 2017
Publication date	Dec 13, 2018
Grant date	—

Abstract

A semiconductor device includes a substrate having a device isolation region defining an active region. An active fin is positioned in the active region. A gate structure overlaps the active fin along a direction orthogonal to an upper surface of the substrate and extends in a second direction intersecting the first direction, A source/drain region is disposed on the active fin. A contact plug is connected to the source/drain region and overlaps the active fin. A metal via is positioned at a first level above the substrate higher than an upper surface of the contact plug and spaced apart from the active fin. A metal line is positioned at a second level above the substrate, higher than the first level and connected to the metal via. A via connection layer extends from an upper portion of the contact plug and is connected to the metal via.

First claim

1 . A semiconductor device, comprising:
a substrate having a device isolation region defining an active region; an active fin positioned in the active region and extended in a first direction; a gate structure overlapping the active fin along a direction orthogonal to an upper surface of the substrate and extended in a second direction intersecting the first direction; a source/drain region disposed on the active fin; a contact plug connected to the source/drain region, and overlapping the active region along the direction orthogonal to the upper surface of the substrate; a metal via positioned at a first level above the substrate, higher than an upper surface of the contact plug, and spaced apart from the active region along the direction orthogonal to the upper surface of the substrate; a metal line positioned at a second level above the substrate, higher than the first, level, and connected to the metal via; and a via connection layer extended from an upper portion of the contact plug and connected to the metal via.

2 . The semiconductor device of claim 1 , wherein the via connection layer is positioned at a level between the upper surface of the contact plug and the first level

3 . The semiconductor device of claim 2 , further comprising:
a first conductive barrier disposed on a side surface and a lower surface of the contact plug, and a second conductive harrier disposed on a side surface and a lower surface of the via connection layer, wherein a portion of the second conductive barrier is positioned between the contact plug and the via connection layer.

4 . The semiconductor device of claim 1 , wherein the upper surface of the contact plug is substantially coplanar with an upper surface of the via connection layer.

5 . The semiconductor device of claim 1 , wherein the via connection layer is integrated with the contact plug.

6 . The semiconductor device of claim 5 , wherein the via connection layer includes a same material as a material included in the contact plug.

7 . The semiconductor device of claim 1 , wherein the via connection layer is positioned at substantially a same level as an upper surface of the gate structure.

8 . The semiconductor device of claim 1 , wherein the contact plug includes a first contact, plug and a second contact plug connected to the source/drain region provided as source/drain regions, respectively, with the gate structure positioned therebetween,
and wherein the contact plug further includes a jumping connection layer positioned at substantially a same level as the via connection layer, and connecting the first contact plug to the second contact plug.

9 . The semiconductor device of claim 1 , wherein the via connection layer includes a first portion extended in one direction and a second portion extended in another direction intersecting the one direction.

10 . The semiconductor device of claim 1 , wherein the contact plug includes a plurality of contact plugs, and

the via connection layer is commonly connected to an upper portion of the plurality of contact plugs and extended to the metal via.

11 . The semiconductor device of claim 1 , wherein the via connection layer and the contact plug are formed of a same material.

12 . The semiconductor device of claim 11 , wherein the via connection layer and the contact plug each include tungsten (W), cobalt (Co), titanium (Ti), alloys thereof, or a combinations thereof.

13 - 15 . (canceled)

16 . The semiconductor device of claim 1 , further comprising
an additional metal via positioned at the first level, higher than the upper surface of the contact plug, and positioned at the upper surface of the active region along the direction orthogonal to the upper surface of the substrate, an additional metal line positioned at the second level, higher than the first level, and connected to the metal via, and an additional via connection layer connecting the additional metal line to the metal line.

17 - 18 . (canceled)

19 . A semiconductor device, comprising:
an active region having an upper surface in which a plurality of active fins are defined; a gate structure overlapping at least one active fin of the plurality of active fins along a direction orthogonal to an upper surface of the substrate; a source/drain region disposed on the plurality of active fins; a contact plug having a lower surface connected to the source/drain region; a metal via spaced apart from the contact plug along the direction orthogonal to the upper surface of the substrate and positioned at a first level above the substrate, higher than an upper surface of the contact plug; a metal line positioned at a second level, higher than the first level, and connected to the metal via; and a via connection layer having an upper surface substantially coplanar with the upper surface of the contact plug, and extended from an upper portion of the contact plug and connected to the metal via.

20 . The semiconductor device of claim 19 , wherein the via connection layer is formed of a same material as a material of the contact plug.

21 . The semiconductor device of claim 19 , wherein the via connection layer is positioned at substantially a same level as an upper surface of the gate structure.

22 . The semiconductor device of claim 19 , wherein the contact plug includes a first contact plug and a second contact plug connected to the source/drain region provided as source/drain regions, respectively, with the gate structure positioned therebetween, and
wherein the contact plug further includes a jumping connection layer disposed along an upper surface of the gate structure and connecting the first contact plug to the second contact plug.

23 . The semiconductor device of claim 19 , wherein the jumping connection layer is positioned at substantially a same level as the via connection layer.

24 . A semiconductor device, comprising:
a substrate including a first active region and a second active region; a first active fin positioned in the first active region; a first source/drain region disposed on the first active fin; a first contact plug positioned above the first source/drain region; a first via connection layer positioned above the first contact plug, wherein the first via connection layer includes a first portion overlapping the first contact plug along a direction orthogonal to an upper surface of the substrate, and a second portion spaced apart from the first contact plug along the direction orthogonal to the upper surface of the substrate; a first metal via disposed on the second portion of the first via connection layer; a first metal line disposed on the first metal via; a second active fin positioned in the second active region; a second source/drain region disposed on the second active fin; a second contact plug positioned above the second source/drain region; a second via connection layer positioned above the second contact plug and overlapping the second contact plug along the direction orthogonal to the upper surface of the substrate; a second metal via disposed on the second via connection layer; and a second metal line disposed on the second metal via.

25 . The semiconductor device of claim 24 , wherein the first metal via is positioned between the first active region and the second active region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Seul Ki
• Shin Heon Jong
• Jun Hwi Chan
• Gwak Min Chan

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P50/268

  of silicon-containing layers · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/4446

  Refractory-metal alloys · CPC title