Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9530737-B1
Application number	US-201514868377-A
Country	US
Kind code	B1
Filing date	Sep 28, 2015
Priority date	Sep 28, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming a dielectric layer over a substrate;
forming a first pattern and a second pattern in the first interlayer dielectric layer, the first pattern having a width greater than a width of the second pattern;
forming a first metal layer in the first pattern and the second pattern;
forming a second metal layer in the first pattern; and
performing a planarization operation on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed, wherein:
a metal material of the first metal layer is different from a metal material of the second metal layer,
the first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer, and
the metal material of the first metal layer includes at least one of Co, Ru and Ag.

2. The method of claim 1 , further comprising, before forming the first metal layer, forming a third metal layer in the first and second patterns and over an upper surface of the dielectric layer.

3. The method of claim 1 , wherein:
the metal material of the second metal layer includes one of Cu, Co, Al and Ag.

4. The method of claim 1 , wherein:
the metal material of the first metal layer includes Co, and
the metal material of the second metal layer includes Cu.

5. The method of claim 2 , wherein the third metal layer includes one of TiN and TaN.

6. A method for manufacturing a semiconductor device, comprising:
forming a dielectric layer over a substrate;
forming a first pattern and a second pattern in the first interlayer dielectric layer, the first pattern having a width greater than a width of the second pattern;
forming a first metal layer in the first pattern and the second pattern;
forming a second metal layer in the first pattern; and
performing a planarization operation on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed, wherein:
a metal material of the first metal layer is different from a metal material of the second metal layer,
the first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer, and
the planarization operation includes:
a first planarization operation, in which an etching rate for the second metal layer is higher than an etching rate for the first metal layer; and
a second planarization operation performed after the first planarization operation, in which the etching rate for the second metal layer is smaller than the etching rate for the first metal layer.

7. The method of claim 6 , wherein the first planarization operation is performed such that the first metal layer is not exposed.

8. The method of claim 6 , wherein:
the method further comprises, before forming the first metal layer, forming a third metal layer in the first and second patterns and over an upper surface of the dielectric layer, and
the second planarization operation uses the third metal layer disposed over the upper surface of the dielectric layer as an etching stopper.

9. The method of claim 8 , wherein the planarization operation includes:
a third planarization operation performed after the second planarization operation,
wherein the third metal layer disposed over the upper surface of the dielectric layer is removed by the third planarization operation.

10. The method of claim 1 , wherein the first pattern and the second pattern are recesses laterally extending in a plan view and used for metal wirings to electrically connect different elements located at laterally different positions.

11. The method of claim 1 , wherein the first pattern and the second pattern are holes vertically extending in the dielectric layer and used for contact plugs connecting an upper layer element and a lower layer element.

12. The method of claim 1 , further comprising performing a heat treatment at a temperature from 200° C. to 500° C. after the forming the first metal layer and before the forming the second metal layer.

13. The method of claim 1 , further comprising performing a heat treatment at a temperature from 200° C. to 500° C. after the forming the second metal layer and before the planarization operation is performed.

14. A semiconductor device, comprising:
a first metal wiring and a second metal wiring, which are formed in a same interlayer dielectric layer disposed over a substrate, the first metal wiring and the second metal wiring being disposed on a same wiring layer disposed in the interlayer dielectric layer, wherein:
the first metal wiring includes at least a first metal layer made of a first material and a second metal layer made of a second metal material disposed over the first metal layer,
the second metal wiring includes a first metal layer made of the first metal material but does not include any metal layer made of the second metal material,
the first metal material is different from the second metal material, and
the metal material of the first metal layer includes at least one of one of Co, Ru and Ag.

15. The semiconductor device of claim 14 , wherein:
the first metal wiring further includes a barrier metal layer made of a third metal material disposed under the first metal layer of the first metal wiring, and
the second metal wiring further includes a barrier metal layer made of the third metal material disposed under the first metal layer of the second metal wiring.

16. The semiconductor device of claim 14 , wherein:
the second metal material includes one of Cu, Co, Al and Ag.

17. The semiconductor device of claim 14 , wherein:
the metal material of the first metal layer includes Co, and
the metal material of the second metal layer includes Cu.

18. The semiconductor device of claim 15 , wherein the third metal material includes one of TiN and TaN.

19. A semiconductor device, comprising:
a first metal wiring and a second metal wiring, which are formed in an interlayer dielectric layer disposed over a substrate, the first metal wiring and the second metal wiring being disposed on a same wiring layer, wherein:
the first metal wiring includes a layered structure having more than one conductive layer,
the second metal wiring includes a layered structure having one or more conductive layers,
the layered structure of the first metal wiring is different from the layered structure of the second metal wiring, and
at least one of the more than one conductive layer of the first metal wiring includes at least one of Co, Ru and Ag.

20. The semiconductor device of claim 19 , wherein:
a number of conductive layers in the first metal wring is greater than a number of conductive layers in the second metal wiring.

21. The semiconductor device of claim 19 , wherein the metal material of the first metal layer includes Co.

22. The semiconductor device of claim 19 , wherein a difference between the number of conductive layers in the first metal wring and the number of conductive layers in the second metal wiring is one.

23. The method of claim 6 , wherein in the first planarization operation, the etching rate for the second metal layer is twice or more than the etching rate for the first metal layer.

24. The method of claim 6 , wherein

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Fu Shih-Kang
• Wu Hsien-Chang
• Su Li-Lin
• Lee Ming-Han
• Shue Shau-Lin

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/264

  by chemical means · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/0526

  by thermal treatment thereof · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title