Semiconductor interconnect structure

Patent metadata

Field	Value
Publication number	US-10096544-B2
Application number	US-201213464055-A
Country	US
Kind code	B2
Filing date	May 4, 2012
Priority date	May 4, 2012
Publication date	Oct 9, 2018
Grant date	Oct 9, 2018

Abstract

The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first conductive line feature having a topmost surface, wherein the first conductive line feature is formed in a first dielectric layer disposed on a semiconductor substrate having a plurality of microelectronic components formed in the semiconductor substrate;
a first via conductor disposed over the first conductive line feature,
wherein a first portion of a bottom surface of the first via conductor interfaces a portion of the topmost surface of the first conductive line feature and a second portion of the bottom surface of the first via conductor interfaces the first dielectric layer;

a second via conductor disposed over the first via conductor and the second via conductor having a bottom surface, wherein a first portion of the bottom surface of the second via conductor interfaces a top surface of the first via conductor and a second portion of the second via conductor interfaces a second dielectric layer adjacent the first via conductor; and
a second conductive line feature disposed over and interfacing a top surface of the second via conductor,
wherein the second conductive line feature has a bottommost surface with a first portion interfaces a first portion of a top surface of the second via conductor, wherein a second portion of the top surface of the second via conductor interfaces a third dielectric layer, the third dielectric layer over the second dielectric layer, and wherein the first portion of the top surface of the second via conductor is coplanar with the second portion of the top surface of the second via conductor; and
wherein the first conductive line feature and the second conductive line feature are offset such that the topmost surface of the first conductive line feature is not directly underneath the bottommost surface of the second conductive line feature;
wherein the interface of the first portion of the top surface of the second via conductor and the bottommost surface of the second conductive line feature has a first length, and the interface between the first portion of the bottom surface of the first via conductor and the portion of the topmost surface of the first conductive line feature has a second length, the first length greater than the second length; and

the first conductive line feature is in a first interconnect layer denoted Mx of an interconnect structure of the semiconductor device;
the second conductive line feature is in a second interconnect layer of the interconnect structure of the semiconductor device above the first interconnect layer denoted Mx+1, wherein x is equal to an whole number equal to 1; and
wherein the first conductive line feature, the first via conductor, the second via conductor and the second conductive line feature provide electrical routing between the microelectronic components of the semiconductor substrate.

2. The semiconductor device of claim 1 , wherein the first via conductor and the second via conductor are offset such that a portion of a bottommost surface of the second via conductor is free from contact by a topmost surface of the first via conductor.

3. The semiconductor device of claim 1 , wherein the first via conductor and the second via conductor are shaped differently.

4. The semiconductor device of claim 1 , wherein the first via conductor and the second via conductor each have an approximately trapezoidal shape.

5. The semiconductor device of claim 1 , further comprising: an etch-stop layer disposed near an interface between the first via conductor and the second via conductor.

6. The semiconductor device of claim 1 , wherein the top surface of the first via conductor includes a second portion interfacing an etch stop layer disposed between the second dielectric layer and the third dielectric layer.

7. The semiconductor device of claim 1 , wherein the first dielectric layer extends to a top surface of the semiconductor substrate.

8. The semiconductor device of claim 7 , wherein the first dielectric layer includes a plurality of dielectric compositions.

9. A semiconductor structure, comprising:
a semiconductor substrate having an interconnect structure disposed thereon, the interconnect structure providing interconnections between features formed in the semiconductor substrate, the interconnect structure including:
a first interconnect layer containing a first metal line in a first dielectric layer and extending parallel to a top surface of the semiconductor substrate providing electrical routing in a horizontal direction;

a second dielectric layer located over the first metal line and the first dielectric layer;
a first sub-via conductor having a planar first bottommost surface, the planar first bottommost surface having a first portion interfacing to a topmost surface of the first metal line and a second portion of the planar first bottommost surface interfacing the first dielectric layer;
a second sub-via conductor having a planar second bottommost surface, a first portion of the planar second bottommost surface interfacing to the first sub-via conductor and a second portion of the planar second bottommost surface interfacing the second dielectric layer, the second sub-via conductor being different from the first sub-via conductor, wherein the first sub-via conductor is positioned above the first metal line and the second sub-via conductor is positioned above the first sub-via conductor; and

a second interconnect layer located over the second dielectric layer and containing a second metal line extending parallel to the top surface of the semiconductor substrate and providing routing in the horizontal direction and interfacing the second sub-via conductor,
wherein a first portion of a planar topmost surface of the second sub-via conductor interfaces a first portion of a bottommost surface of the second metal line, and a second portion of the planar topmost surface of the second sub-via conductor interfaces a third dielectric layer, wherein a first length of the first portion of the planar topmost surface of the second sub-via conductor is greater than a second length of the first portion of the planar first bottommost surface of the first sub-via conductor that interfaces the topmost surface of the first metal line;
wherein the second interconnect layer is an adjacent interconnect layer to the first interconnect layer; and
wherein a topmost surface of the first metal line is not directly underneath the bottommost surface of the second metal line.

10. The semiconductor structure of claim 9 , wherein the first sub-via conductor and the second sub-via conductor have different geometries.

11. The semiconductor structure of claim 9 , further comprising: an etch-stop layer located near and circumferentially surrounding an interface between the first sub-via conductor and the second sub-via conductor.

12. The semiconductor structure of claim 9 , wherein: from a top view perspective, the first sub-via conductor is free of being enclosed by the first metal line, or the second sub-via conductor is free of being enclosed by the second metal line.

13. The semiconductor structure of claim 9 , wherein the features formed in the semiconductor substrate include doped features.

14. A semiconductor device, comprising:
a first conductive component disposed in a first dielectric material over a semiconductor substrate, wherein the first conductive component is a first metal line providing a horizontal routing of an electrical signal;
a first via conductor in a third dielectric material and disposed over the first conductive component,
wherein a first portion of a bottom surface of the first via con

Assignees

• Lai Chih Ming
• Huang Wen Chun
• Liu Ru Gun
• Chen Pi Tsung
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chih-Ming
• Huang Wen-Chun
• Liu Ru-Gun
• Chen Pi-Tsung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/01

  Manufacture or treatment · CPC title