Semiconductor device

Patent metadata

Field	Value
Publication number	US-12199040-B2
Application number	US-202117180491-A
Country	US
Kind code	B2
Filing date	Feb 19, 2021
Priority date	Jul 14, 2020
Publication date	Jan 14, 2025
Grant date	Jan 14, 2025

Abstract

Disclosed is a semiconductor device comprising a first logic cell and a second logic cell on a substrate. Each of the first and second logic cells includes a first active region and a second active region that are adjacent to each other in a first direction, a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction, and a first metal layer on the gate electrode. The first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other. The first and second logic cells are adjacent to each other in the second direction along the first and second power lines. The first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first logic cell and a second logic cell on a substrate, wherein each of the first and second logic cells includes:
a first active region and a second active region that are adjacent to each other in a first direction;
a gate electrode that runs across the first and second active regions and extends lengthwise in the first direction; and
a first metal layer on the gate electrode,
wherein the first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other,

wherein the first and second logic cells are adjacent to each other in the second direction along the first and second power lines,
wherein the first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell,
wherein the first metal layer of the first logic cell further includes one or more first lower lines aligned on first line tracks between the first and second power lines,
wherein the first metal layer of the second logic cell further includes one or more second lower lines aligned on second line tracks between the first and second power lines,
wherein the first and second line tracks extend in the second direction,
wherein a distance between different sets of adjacent first line tracks of the first logic cell is the same,
wherein a distance between different sets of adjacent second line tracks of the second logic cell is the same,
wherein at least one of the first line tracks of the first logic cell is disposed at a center in the first direction of the one or more first lower lines,
wherein at least one of the second line tracks of the second logic cell is disposed at a center in the first direction of the one or more second lower lines, and
wherein the second line tracks are offset in the first direction from corresponding first line tracks, respectively.

2. The semiconductor device of claim 1 , wherein each of the first and second logic cells further includes:
a first active pattern and a second active pattern on the first active region and the second active region, respectively;
a first source/drain pattern and a second source/drain pattern on an upper portion of the first active pattern and an upper portion of the second active pattern, respectively, the first and second source/drain patterns being adjacent to one side of the gate electrode;
an active contact on the first and second source/drain patterns; and
a gate contact on the gate electrode,
wherein the one or more first lower lines are electrically connected to at least one of the active contact and the gate contact on the first logic cell, and
wherein the one or more second lower lines are electrically connected to at least one of the active contact and the gate contact on the second logic cell.

3. The semiconductor device of claim 2 , wherein:
the active contact of each of the first and second logic cells extends lengthwise in the first direction and electrically connects the first and second source/drain patterns to each other, and
a length in the first direction of the active contact on the first logic cell is greater than a length in the first direction of the active contact on the second logic cell.

4. The semiconductor device of claim 2 , wherein the first active pattern on each of the first and second logic cells is one of a plurality of first active patterns,
wherein the number of the plurality of first active patterns on the first logic cell is greater than the number of the plurality of first active patterns on the second logic cell.

5. The semiconductor device of claim 2 , wherein the first active pattern on each of the first and second logic cells includes a plurality of first channel patterns that are vertically stacked and spaced apart from each other,
wherein an uppermost one of the first channel patterns on the first logic cell has a first width in the first direction,
wherein an uppermost one of the first channel patterns on the second logic cell has a second width in the first direction, and
wherein the first width is greater than the second width.

6. The semiconductor device of claim 1 , wherein each of the first and second logic cells further includes a cutting pattern on an end of the gate electrode in the first direction, and
wherein a width in the first direction of the cutting pattern on the first logic cell is greater than a width in the first direction of the cutting pattern on the second logic cell.

7. The semiconductor device of claim 1 , wherein a length in the first direction of the gate electrode on the first logic cell is greater than a length in the first direction of the gate electrode on the second logic cell.

8. The semiconductor device of claim 1 , wherein a width in the first direction of the first power line on the first logic cell is less than a width in the first direction of the first power line on the second logic cell.

9. The semiconductor device of claim 1 , wherein a pitch between the first line tracks is substantially the same as a pitch between the second line tracks.

10. The semiconductor device of claim 1 , wherein the number of the first line tracks is greater than the number of the second line tracks.

11. A semiconductor device, comprising:
a first logic cell and a second logic cell on a substrate, wherein each of the first and second logic cells includes:
a first active region and a second active region that are adjacent to each other in a first direction;
a first active pattern and a second active pattern on the first active region and the second active region, respectively;
a gate electrode that runs across the first and second active patterns and extends lengthwise in the first direction; and
a first metal layer on the gate electrode,

wherein the first metal layer includes a first power line and a second power line that extend lengthwise in a second direction perpendicular to the first direction, and are parallel to each other,
wherein the first and second logic cells are adjacent to each other in the second direction along the first and second power lines,
wherein the first and second active regions extend lengthwise in the second direction from the first logic cell to the second logic cell,
wherein the first active pattern of each of the first and second logic cells includes a plurality of first channel patterns that are vertically stacked and spaced apart from each other,
wherein an uppermost one of the first channel patterns on the first logic cell has a first width in the first direction,
wherein an uppermost one of the first channel patterns on the second logic cell has a second width in the first direction, and
wherein the first width is greater than the second width.

12. The semiconductor device of claim 11 , wherein the gate electrode surrounds each of the stacked first channel patterns.

13. The semiconductor device of claim 11 , wherein:
the first metal layer of the first logic cell further includes one or more first lower lines aligned on first line tracks between the first and second power lines,
the first metal layer of the second logic cell further includes one or more second lower lines aligned on second line tracks between the first and second power lines, and
the number of the first line tracks is greater than the number of the second line tracks.

14. The semiconductor device of claim 11 , wherein a cell height in the first direction of the first logic cell is greater than a cell height in the first direction of the second logic cell.

Assignees

• Samsung Electronics Co Ltd

Inventors

• You Hyeongyu
• YU Jisu
• Seo Jae-Woo
• Lim Seung Man

Classifications

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title