Semiconductor device including a field effect transistor

Patent metadata

Field	Value
Publication number	US-10916535-B2
Application number	US-201916727280-A
Country	US
Kind code	B2
Filing date	Dec 26, 2019
Priority date	Jun 1, 2017
Publication date	Feb 9, 2021
Grant date	Feb 9, 2021

Abstract

A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a plurality of fins;
a plurality of gate electrodes intersecting the plurality of fins;
an active contact electrically connected to the plurality of fins;
a plurality of vias including a first via, a second via and a third via; and
a plurality of interconnection lines on the plurality of vias,
wherein the plurality of interconnection lines include a first interconnection line on both the first via and the second via, and a second interconnection line on the third via,
wherein the first interconnection line is electrically connected to the active contact through the first via, and
wherein the second and third vias are disconnected to the active contact and the plurality of gate electrodes.

2. The semiconductor device of claim 1 , wherein the third via vertically overlaps a first gate electrode of the plurality of gate electrodes.

3. The semiconductor device of claim 1 , further comprising a gate contact electrically connected to a second gate electrode of the plurality of gate electrodes,
wherein third via is spaced apart from the second and third gate electrodes with an interlayer insulating layer interposed therebetween.

4. The semiconductor device of claim 1 , wherein a width of the third via is greater than a width of the second via.

5. The semiconductor device of claim 1 , wherein the plurality of fins and at least one of the plurality of gate electrodes constitute a high-voltage transistor.

6. The semiconductor device of claim 1 , further comprising an interlayer insulating layer on the active contact and the plurality of gate electrodes,
wherein the plurality of vias are disposed on the interlayer insulating layer, and
wherein a top surface of the interlayer insulating layer covers bottom surfaces of the second and third vias.

7. The semiconductor device of claim 1 , further comprising a connection structure between the active contact and the first via.

8. The semiconductor device of claim 1 , wherein the first interconnection line has an extension extending in a direction parallel with an extending direction of the gate electrodes, and
wherein the second via is disposed under the extension.

9. The semiconductor device of claim 1 , wherein the first via is a regular via, and
wherein each of the second and third vias is a dummy via.

10. The semiconductor device of claim 1 , wherein the plurality of fins includes:
a first fin on a PMOSFET region; and
a second fin on an NMOSFET region,
wherein the first and second fins each extend in a first direction, and
wherein each of the plurality of gate electrodes extend in a second direction intersecting the first direction.

11. A semiconductor device including a standard cell, the semiconductor device comprising:
a substrate;
a plurality of FinFETs on the substrate, the plurality of FinFETs constitute a logic circuit of the standard cell;
an interlayer insulating layer on the plurality of FinFETs,
a plurality of vias on the interlayer insulating layer, the plurality of vias including a first via, a second via and a third via; and
a plurality of interconnection lines on the plurality of vias,
wherein the plurality of interconnection lines comprise a first interconnection line on both the first via and the second via, and a second interconnection line on the third via,
wherein the first interconnection line is electrically connected to at least one of the plurality of FinFETs through the first via, and
wherein the second and third vias are disconnected to the plurality of FinFETs.

12. The semiconductor device of claim 11 , wherein the third via vertically overlaps a gate electrode of at least one of the plurality of FinFETs.

13. The semiconductor device of claim 12 , wherein a width of the third via is greater than a width of the second via.

14. The semiconductor device of claim 11 , wherein the plurality of vias further includes a fourth via disposed under the second interconnection line,
wherein the second interconnection line is electrically connected to at least one of the plurality of FinFETs through the fourth via.

15. The semiconductor device of claim 11 , wherein the first via is a regular via, and
wherein each of the second and third vias is a dummy via.

16. A semiconductor device comprising:
a substrate;
a substrate including a plurality of fins;
a plurality of gate electrodes intersecting the plurality of fins;
a first interlayer insulating layer on the plurality of gate electrodes;
a second interlayer insulating layer on the first interlayer insulating layer;
a third interlayer insulating layer on the second interlayer insulating layer;
a connection structure in the first interlayer insulating layer;
a plurality of vias in the second interlayer insulating layer, the plurality of vias including a first via, a second via and a third via; and
an interconnection line in the third interlayer insulating layer,
wherein the first via is disposed between the interconnection line and the connection structure and electrically connects the interconnection line to the connection structure, and
wherein the second and third vias are spaced apart from the connection structure, such that a top surface of the first interlayer insulating layer covers bottom surfaces of the second and third vias.

17. The semiconductor device of claim 16 , wherein the third via vertically overlaps at least one of the plurality of gate electrodes.

18. The semiconductor device of claim 17 , wherein a width of the third via is greater than a width of the second via.

19. The semiconductor device of claim 17 , wherein the plurality of fins and the at least one of the plurality of gate electrodes constitute a high-voltage transistor.

20. The semiconductor device of claim 16 , wherein the first via is a regular via, and wherein each of the second and third vias is a dummy via.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Do Jung-Ho
• Rim Woojin
• YU Jisu
• Jung Jonghoon

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title