Semiconductor circuit with metal structure and manufacturing method

Patent metadata

Field	Value
Publication number	US-10756114-B2
Application number	US-201815964216-A
Country	US
Kind code	B2
Filing date	Apr 27, 2018
Priority date	Dec 28, 2017
Publication date	Aug 25, 2020
Grant date	Aug 25, 2020

Abstract

The semiconductor structure includes a semiconductor substrate having active regions; field-effect devices disposed on the semiconductor substrate, the field-effect devices including gate stacks with elongated shape oriented in a first direction; a first metal layer disposed over the gate stacks, the first metal layer including first metal lines oriented in a second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, the second metal layer including second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, the third metal layer including third metal lines oriented in the second direction. The first, second, and third metal lines have a first thickness T 1 , a second thickness T 2 , and t a third thickness T 3 , respectively. The second thickness is greater than the first thickness and the third thickness.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor substrate having active regions;
a plurality of field-effect devices disposed on the semiconductor substrate, wherein the field-effect devices include gate stacks with elongated shape oriented in a first direction;
a first metal layer disposed over the gate stacks, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction that is orthogonal to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction,
wherein, the first metal lines have a first minimum pitch P 1 ;
the second metal lines have a second minimum pitch P 2 ;
the third metal lines have a third minimum pitch P 3 ;
the first minimum pitch P 1 equals to the third minimum pitch P 3 ; and
the second minimum pitch P 2 is greater than the third minimum pitch P 3 and the first minimum pitch P 1 .

2. The semiconductor structure of claim 1 , further comprising:
a source/drain (S/D) feature formed on one of the active regions;
a contact landing on the S/D feature; and
a via feature landing on the contact and underlying the first metal lines, wherein
the S/D feature is electrically connected to one of the first metal lines through the contact and via feature; and
the contact is different from the via feature in composition.

3. The semiconductor structure of claim 2 , wherein
the contact includes a tantalum nitride layer, a tantalum layer and a cobalt layer;
the via feature includes tungsten; and
the first metal lines include copper.

4. The semiconductor structure of claim 2 , wherein the first metal lines and the via feature are formed in a dual damascene process and both include ruthenium.

5. The semiconductor structure of claim 1 , wherein
wherein the first metal lines have a first thickness T 1 , the second metal lines have a second thickness T 2 , and the third metal lines have a third thickness T 3 , and wherein the second thickness is greater than the first thickness and the third thickness.

6. The semiconductor structure of claim 5 , wherein a first thickness ratio T 2 /T 1 is greater than 1.2 and a second thickness ratio T 2 /T 3 is equal to or greater than 1.2.

7. The semiconductor structure of claim 6 , further comprising one standard cell, wherein
the gate stacks and the second metal lines are configured in the standard cell;
the gate stacks have a fourth minimum pitch P4; and
a pitch ratio P4/P2 equals to 1.

8. The semiconductor structure of claim 7 , wherein
the gate stacks span a first width W 1 along the second direction;
the second metal lines span a second width W 2 along the second direction; and
a width ratio W 1 /W 2 is not equal to 1.

9. The semiconductor structure of claim 8 , wherein
the first metal lines have a third width W 3 ;
the third metal lines have a fourth width W 4 ; and
the third width W 3 equals to the forth width W 4 .

10. The semiconductor structure of claim 6 , wherein a third thickness ratio T 3 /T 1 equals to 1.

11. A semiconductor structure, comprising:
a semiconductor substrate having a first region for a first standard cell and a second region for a second standard cell, wherein each of the first and second standard cells includes a n-type field-effect transistor and a p-type field effect transistor;
a first active region and a second active region formed on the semiconductor substrate, wherein the first and second active regions are isolated from each other by an isolation feature, and wherein the first and second standard cells share an edge on the isolation feature;
a first and second gate stacks with elongated shape oriented in a first direction, wherein the first gate stack is disposed on the first active region and the second gate stack is disposed in the second active region;
a first and second interconnection gate stacks oriented in the first direction, wherein the first interconnection gate stack is partially landing on the first active region and partially landing on the isolation feature, and the second interconnection gate stack is partially landing on the second active region and partially landing on the isolation feature;
a first metal layer disposed over the first and second gate stacks, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction being orthogonal to the first direction;
a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and
a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction,
wherein the first metal lines have a first thickness T 1 , the second metal lines have a second thickness T 2 , the third metal lines have a third thickness T 3 , and wherein a first thickness ratio T 2 /T 1 is equal to or greater than 1.2, a second thickness ratio T 2 /T 3 is equal to or greater than 1.2: and
wherein the gate stacks have a first minimum pitch P 1 , the second metal lines have a second minimum pitch P 2 , a pitch ratio P 1 /P 2 equals to 1, the first metal lines have a third minimum pitch P 3 , the third metal lines have a fourth minimum pitch P 4 , the third minimum pitch P 3 equals to the fourth minimum pitch P 4 , and the second minimum pitch P 2 is greater than the third minimum pitch P 3 and the fourth minimum pitch P 4 .

12. The semiconductor structure of claim 11 , wherein a third thickness ratio T 3 /T 1 equals to 1.

13. The semiconductor structure of claim 12 , further comprising a first contact and a second contact landing on opposite ends of the first interconnection gate stack, respectively, wherein the first contact is connected to a first one of the first metal lines and the second contact is connected to a second one of the first metal lines, the first interconnection gate stack function as a conductive path for local interconnection.

14. The semiconductor structure of claim 12 ,
the gate stacks span a first width W 1 along the second direction;
the second metal lines span a second width W 2 along the second direction;
a first width ratio W 1 /W 2 is not equal to 1.

15. The semiconductor structure of claim 14 , wherein
the first metal lines span a third minimum pitch P 3 along the first direction;
the third metal lines span a fourth minimum pitch P 4 along the first direction;
the third minimum pitch P 3 equals to the fourth minimum pitch P 4 ; and
the second minimum pitch P 2 is greater than the third minimum pitch P 3 and the fourth minimum pitch P 4 .

16. The semiconductor structure of claim 11 , further comprising:
a source/drain (S/D) feature formed on the first active regions;
a contact landing on the S/D feature; and
a via feature landing on the contact and underlying the first metal lines, wherein
the S/D feature is electrically connected to one of the first metal lines through the contact and via feature; and
the contact is different from the via feature in composition.

17. The semiconductor structure of claim 16 , wherein
the contact includes a tantalum nitride layer, a tantalum layer and a cobalt layer;
the via feature includes tungsten; and
the first metal lin

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liaw Jhon Jhy

Classifications

• H10W20/4424

  Copper alloys · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/0698

  Local interconnections · CPC title