System-on-chip devices and methods of designing a layout therefor

Patent metadata

Field	Value
Publication number	US-2016254256-A1
Application number	US-201615046200-A
Country	US
Kind code	A1
Filing date	Feb 17, 2016
Priority date	Feb 26, 2015
Publication date	Sep 1, 2016
Grant date	—

Abstract

A system-on-chip device may include a substrate with an active pattern, a gate electrode crossing the active pattern and extending in a first direction, and a first metal layer electrically connected to the active pattern and the gate electrode. The first metal layer may include a first metal line extending in the first direction and a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction. The first and second metal lines may include first and second sidewalls parallel to the second direction, the first and second sidewalls may face each other, and the first sidewall may have a length that is two or three times a minimum line width.

First claim

What is claimed is:

1 . A system-on-chip device, comprising:
a substrate with an active pattern; a gate electrode crossing the active pattern and extending in a first direction parallel to a top surface of the substrate; and a first metal layer electrically connected to the active pattern and the gate electrode, wherein: the first metal layer comprises:
a first metal line extending in the first direction; and
a second metal line spaced apart from the first metal line in the first direction to extend in a second direction crossing the first direction,
the first metal line comprises a first sidewall parallel to the second direction, the second metal line comprises a second sidewall parallel to the second direction, the first sidewall and the second sidewall face each other, and the first sidewall has a length that is two or three times a minimum line width.

2 . The device of claim 1 , wherein the minimum line width is a minimum width, in the first direction, of the second metal line.

3 . The device of claim 1 , wherein:
the first metal layer further comprises a third metal line extending in the second direction, the second metal line and the third metal line are spaced apart from each other in the first direction by a first distance, and the first sidewall and the second sidewall are spaced apart from each other by a second distance that is in a range from about 1 to about 1.2 times the first distance.

4 . The device of claim 1 , wherein:
the first metal layer comprises:
a third metal line extending in the second direction; and
a fourth metal line spaced apart from the third metal line in the first direction and extending in the first direction,
the third metal line comprises a third sidewall parallel to the second direction, the fourth metal line comprises a fourth sidewall parallel to the second direction, the third sidewall and the fourth sidewall face each other, the fourth sidewall has a length shorter than that of the first sidewall, the first sidewall and the second sidewall are spaced apart from each other by a first distance, and the third sidewall and the fourth sidewall are spaced apart from each other by a second distance greater than the first distance.

5 . The device of claim 1 , further comprising:
a second metal layer on the first metal layer, wherein: the second metal layer comprises third metal lines extending in the first direction and parallel to each other, and one of the third metal lines is electrically connected to the first metal line to provide pin areas for a routing.

6 . The device of claim 5 , wherein:
the second metal line comprises a plurality of metal line patterns spaced apart from each other in the first direction, and another of the third metal lines is disposed to electrically connect the metal line patterns spaced apart from each other.

7 . The device of claim 5 , further comprising:
a third metal layer on the second metal layer, wherein: the third metal layer comprises fourth metal lines extending in the second direction and parallel to each other, and one of the fourth metal lines is coupled to one of the pin areas of the third metal line and is electrically connected to the first metal line.

8 . The device of claim 1 , further comprising:
source/drain regions formed in upper portions of the active pattern and at both sides of the gate electrode; and contacts respectively coupled to the gate electrode and the source/drain regions, wherein the first and second metal lines are electrically connected to the contacts.

9 . A layout design method comprising:
providing a layout pattern for forming a system-on-chip device, in which a plurality of standard cells are provided, wherein: the providing of the layout pattern comprises providing a first metal layout defining a first metal layer, the first metal layout comprises:
a first pattern extending in a first direction; and
a second pattern spaced apart from the first pattern in the first direction to extend in a second direction crossing the first direction,
the first and second patterns, respectively, comprise first and second sidewalls facing each other, and a distance between the first sidewall and the second sidewall is in a range from about 1 to about 1.2 times a minimum separation distance given by a design rule for a layout.

10 . The method of claim 9 , wherein a length of the first sidewall is about 2 to about 3 times a minimum line width given by the design rule.

11 . The method of claim 9 , wherein:
a length of the first sidewall is equal to or greater than a minimum sidewall length, allowing for the first sidewall to be spaced apart from the second sidewall by the minimum separation distance, and the length of the first sidewall is smaller than that of the second sidewall.

12 . The method of claim 9 , wherein the first metal layout further comprises:
a third pattern extending in the first direction; and a fourth pattern spaced apart from the third pattern in the first direction to extend in the second direction, wherein: the third and fourth patterns, respectively, comprise third and fourth sidewalls facing each other, a length of the third sidewall is smaller than that of the first sidewall, and a distance between the third and fourth sidewalls is greater than a distance between the first and second sidewalls.

13 . The method of claim 12 , wherein the length of the third sidewall is in a range from about 1 to about 2 times a minimum line width given by the design rule.

14 . The method of claim 9 , wherein:
the providing of the layout pattern further comprises providing a second metal layout defining a second metal layer and providing a third metal layout defining a third metal layer, the first to third metal layers are sequentially stacked on a substrate, the second metal layout comprises third patterns extending in the first direction and parallel to each other, the third metal layout comprises fourth patterns extending in the second direction and parallel to each other, and the first direction is an extension direction of a gate pattern.

15 . The method of claim 14 , wherein at least one of the third patterns is overlapped with the first pattern and comprises a plurality of pin areas for a routing.

16 . A logic cell comprising:
a substrate with an active pattern for the logic cell, the active pattern being extending in a first direction parallel to a top surface of the substrate; and a first metal layer electrically connected to the active pattern, wherein: the first metal layer comprises:
a first metal line having a first width in the first direction;
a second metal line that is spaced apart from the first metal line in a second direction crossing the first direction by about a minimum spacing according to a layout design rule and having a second width in the second direction that is about one-half the first width or less and about the same as a minimum line width according to the layout design rule, and
a third metal line that is spaced apart from the first metal line on an opposite side of the first metal line with respect to the second direction by the minimum spacing and having the second width in the second direction, wherein:
at least one of the first to third metal lines is electrically connected to the active pattern through a first via extending through a first insulating layer disposed between the active pattern and the first metal layer, and the first metal line is not electrically connected to either of the second and third metal lines through metal connectivi

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sanghoon
• Do Jung-Ho
• Song Taejoong
• Yang Giyoung
• Lee Seungyoung
• Lim Jinyoung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title