Semiconductor package having a high reliability

Patent metadata

Field	Value
Publication number	US-12183718-B2
Application number	US-202418409778-A
Country	US
Kind code	B2
Filing date	Jan 10, 2024
Priority date	Feb 22, 2016
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package, the method comprising:
providing a package substrate and a plurality of semiconductor devices, each of the plurality of semiconductor devices having connection terminals;
stacking the plurality of semiconductor devices on the package substrate at a first temperature, each for a first time;
heating the plurality of semiconductor devices to a second temperature higher than the first temperature;
maintaining the plurality of semiconductor devices at the second temperature for a second time greater than the first time while applying pressure to the plurality of semiconductor devices, so that the connection terminals are reflowed and the plurality of semiconductor devices are bonded to the package substrate; and
molding the plurality of semiconductor devices.

2. The method of claim 1 , wherein the heating of the plurality of semiconductor devices to a second temperature is performed after the stacking of the plurality of semiconductor devices.

3. The method of claim 1 , wherein each of the plurality semiconductor devices have a pre-applied underfill film on a surface.

4. The method of claim 3 , wherein the plurality of semiconductor devices are coupled with each other depending on viscosity of the pre-applied underfill film during the stacking of the plurality of semiconductor devices.

5. The method of claim 3 , wherein during the maintaining the plurality of semiconductor devices at the second temperature for the second time, the pre-applied underfill film is reflowed to form a plurality of underfill fillets, in which at least two neighboring underfill fillets form one continuous structure without an interface therebetween.

6. The method of claim 5 , wherein the pre-applied underfill films are reflowed and form a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices.

7. The method of claim 6 , wherein the at least two neighboring underfill fillets form one continuous structure by a flowing together of corresponding protrusions thereof.

8. The method of claim 5 , further comprising curing the plurality of underfill fillets by cooling the plurality of semiconductor devices, after heating the plurality of semiconductor devices to a second temperature higher than the first temperature.

9. The method of claim 8 , wherein the cooling of the plurality of semiconductor devices is not performed before heating the plurality of semiconductor devices to the second temperature higher than the first temperature.

10. The method of claim 8 , wherein intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate after the curing.

11. The method of claim 1 , wherein the first temperature ranges from about 80° C. to about 100° C.

12. The method of claim 1 , wherein the second temperature ranges from about 220° C. to about 280° C.

13. A method of fabricating a semiconductor package, the method comprising:
providing a package substrate, a first semiconductor device, and a second semiconductor device, the first semiconductor device having a first plurality of connection terminals and the second semiconductor device having a second plurality of connection terminals;
horizontally stacking the first semiconductor device and the second semiconductor device sequentially on the package substrate at a first temperature, each for a first time, to form a stack structure;
simultaneously reflowing the stack structure at a second temperature higher than the first temperature for a second time greater than the first time so that the first semiconductor device and the second semiconductor device are bonded to the package substrate.

14. The method of claim 13 , wherein at least one of the first semiconductor device and the second semiconductor device is a sub-package and the semiconductor package is a package-on-package (PoP) type of package.

15. The method of claim 13 , further comprising curing the stack structure by cooling after the reflowing.

16. The method of claim 13 , wherein the first semiconductor device having a first pre-applied underfill film and the second semiconductor device having a second pre-applied underfill film, after the reflowing the stack structure, the first pre-applied underfill film and the second pre-applied underfill film form one continuous structure without an interface therebetween.

17. The method of claim 15 , further comprising molding the first semiconductor device and the second semiconductor device with molding resin.

18. The method of claim 17 , wherein the upper surface of the second semiconductor device is coplanar with an upper surface of the molding resin at a first plane.

19. The method of claim 18 , wherein the one continuous structure is partially exposed at the first plane.

20. A method of fabricating a semiconductor package, the method comprising:
providing a package substrate and a plurality of semiconductor devices, each of the plurality of semiconductor devices having connection terminals;
stacking the plurality of semiconductor devices on the package substrate at a first temperature, each for a first time, to form a stack structure;
simultaneously reflowing the stack structure at a second temperature higher than the first temperature for a second time greater than the first time so that the plurality of semiconductor devices are bonded to the package substrate; and
curing the stack structure by cooling,
wherein, after the curing, intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Ji-Hwan
• Park Sang-Sick
• Min Tae-Hong
• NAM Geol

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title