Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Semiconductor device and manufacturing method thereof
US8941246B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8941246-B2 |
| Application number | US-201213623249-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 20, 2012 |
| Priority date | Sep 22, 2011 |
| Publication date | Jan 27, 2015 |
| Grant date | Jan 27, 2015 |
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Abstract
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In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor chips and bump electrodes. The interface chip is electrically connected to the interposer substrate via a rewiring layer formed on a surface of an uppermost semiconductor chip in the stacking order or through electrodes provided in the interface chip.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: an interposer substrate having a first surface provided with an external connection terminal and a second surface provided with an internal connection terminal; a chip stacked body, disposed on the second surface of the interposer substrate, having plural semiconductor chips sequentially stacked, the plural semiconductor chips being electrically connected via through electrodes provided in the semiconductor chips excludi…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8941246B2 cover?
- In one embodiment, a semiconductor device includes a chip stacked body disposed on an interposer substrate and an interface chip mounted on the chip stacked body. The chip stacked body has plural semiconductor chips, and is electrically connected via through electrodes provided in the semiconductor chips excluding a lowermost semiconductor chip in a stacking order of the plural semiconductor ch…
- Who is the assignee on this patent?
- Miura Masayuki, Kamoto Taku, Sato Takao, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).