Semiconductor package having a high reliability

Patent metadata

Field	Value
Publication number	US-2017243857-A1
Application number	US-201715439321-A
Country	US
Kind code	A1
Filing date	Feb 22, 2017
Priority date	Feb 22, 2016
Publication date	Aug 24, 2017
Grant date	—

Abstract

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a package substrate; a plurality of semiconductor devices stacked on the package substrate; a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices; and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets, wherein the plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices, and wherein at least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

2 . The semiconductor package of claim 1 , wherein the semiconductor package is included in a digital media player, a solid state disk (SSD), a motor vehicle, a liquid crystal display (LCD) or a graphics processing unit (GPU).

3 . The semiconductor package of claim 1 , wherein an interface is present between the plurality of underfill fillets and the molding resin.

4 . The semiconductor package of claim 1 , wherein intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate.

5 . The semiconductor package of claim 4 , wherein a length of each protrusion of each of the plurality of underfill fillets gets smaller for underfill fillets further away from the package substrate.

6 . The semiconductor package of claim 5 , wherein a height of one of the plurality of underfill fillets is greater than or equal to a height of an upper surface of an uppermost semiconductor device of the plurality of semiconductor devices,
wherein the height of the upper surface of the uppermost semiconductor device of the plurality of semiconductor devices and the height of the one of the plurality of underfill fillets are each measured perpendicularly with respect to a surface of the package substrate.

7 . The semiconductor package of claim 5 , wherein the upper surface of the uppermost semiconductor device of the plurality of semiconductor devices is coplanar with an upper surface of the molding resin at a first plane, and
wherein the plurality of underfill fillets are partially exposed at the first plane.

8 . The semiconductor package of claim 4 , wherein a length of each protrusion of each of the plurality of underfill fillets gets larger for underfill fillets further away from the package substrate.

9 . The semiconductor package of claim 1 , wherein intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices, are substantially equal to each other.

10 . The semiconductor package of claim 9 , wherein a length of each protrusion of each of the plurality of underfill fillets gets larger for underfill fillets further away from the package substrate.

11 . The semiconductor package of claim 1 , wherein the plurality of underfill fillets include a non-conductive film (NCF), a non-conductive paste (NCP), or an anisotropic conductive film (ACF).

12 . The semiconductor package of claim 1 , wherein the plurality of semiconductor devices are sub-packages, wherein at least one of the plurality of semiconductor devices comprises a semiconductor chip, and
wherein the semiconductor package is a package-on-package (PoP) type of package.

13 . A semiconductor package, comprising:
a package substrate; a plurality of semiconductor devices stacked on the package substrate; a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices; and a molding resin surrounding the plurality of semiconductor devices and the plurality of underfill fillets, wherein intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate.

14 . The semiconductor package of claim 13 , wherein at least two adjacent underfill fillets of the plurality of underfill fillets protrude from between two neighboring semiconductor devices and the package substrate or from between three sequentially stacked semiconductor devices,
and wherein the at least two adjacent underfill fillet protrusions form an integrally continuous structure.

15 . The semiconductor package of claim 13 , wherein the plurality of semiconductor devices and the package substrate are electrically connected to each other via a plurality of solder bumps, and
wherein a height of a first solder bump of the plurality of first solder bumps disposed at a first vertical height with respect to a surface of the package substrate is greater than a height of a second solder bump of the plurality of solder bumps disposed at a second vertical height with respect to the surface of the package substrate, wherein the first vertical height is smaller than the second vertical height.

16 . A semiconductor package, comprising:
a package substrate; a first semiconductor device and a second semiconductor device stacked on the package substrate, wherein the first semiconductor device is disposed between the package substrate and the second semiconductor device; a first underfill fillet disposed between the package substrate and the first semiconductor device and a second underfill fillet disposed between the first semiconductor device and the second semiconductor device; and a molding resin covering at least a part of each of the first and second underfill fillets, wherein the first underfill fillet protrudes from an area between the package substrate and the first semiconductor device, the second underfill fillet protrudes from an area between the first semiconductor device and the second semiconductor device, and wherein the protrusion of the first underfill fillet forms one continuous structure with the protrusion of the second underfill fillet.

17 . The semiconductor package of claim 16 , wherein a first spacing between the package substrate and the first semiconductor device is equal to a second spacing between the first semiconductor device and the second semiconductor device, wherein the first and second spacings are measured along a first direction perpendicular to a surface of the package substrate, and
wherein the protrusion of the first underfill fillet is shorter than the protrusion of the second underfill fillet in a second direction that crosses the first direction.

18 . The semiconductor package of claim 16 , wherein a first spacing between the package substrate and the first semiconductor device is larger than a second spacing between the first semiconductor device and the second semiconductor device, wherein the first and second spacings are measured along a first direction perpendicular to a surface of the package substrate, and
wherein the protrusion of the first underfill fillet is shorter to the protrusion of the second underfill fillet in a second direction that crosses the first direction.

19 . The semiconductor package of claim 16 , wherein the protrusion of the first underfill fillet is longer than the protrusion of the second underfill fillet in a direction away from an

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Ji-Hwan
• Park Sang-Sick
• Min Tae-Hong
• NAM Geol

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title