Clock mode determination in a memory system

Patent metadata

Field	Value
Publication number	US-9740407-B2
Application number	US-201615378650-A
Country	US
Kind code	B2
Filing date	Dec 14, 2016
Priority date	Feb 16, 2007
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

First claim

What is claimed is:

1. A system comprising:
a memory controller configured to provide a chip enable signal, a first input signal, a second input signal, common data signals, and setting information for configurable buffers; and
at least one non-volatile memory device communicatively coupled to the memory controller, the at least one non-volatile memory device comprising:
at least two non-volatile memory banks;
a chip enable input port configured to receive the chip enable signal for enabling the at least one non-volatile memory device;
a first input port and a second input port configured to receive the first input signal and the second input signal, respectively, wherein the second input signal is complementary to the first input signal;
a reference voltage input port configured to receive an external reference voltage;
one or more common data ports configured to receive the common data signals carrying command data and at least one of address data and write data, the write data to be latched in synchronization with both rising and falling edges of at least the first input signal and to be programmed into one of the at least two non-volatile memory banks addressable by the address data;
a first configurable input buffer configured to be able to switch from a single ended signaling configuration to a differential signaling configuration, the differential signaling configuration configured to utilize the first input signal and the second input signal as differential signals, and the single ended signaling configuration configured to utilize one of the first input signal and the second input signal as a single ended signal;
a second configurable input buffer configured to be able to utilize the external reference voltage for determining a logic level of the common data signals; and
a configurable output buffer configured to set an output drive strength to provide data from one of the at least two non-volatile memory banks in response to a read command from the memory controller.

2. The system as claimed in claim 1 wherein the first and second input signals are a positive clock input signal and a negative clock input signal respectively.

3. The system as claimed in claim 1 wherein the first and second input signals are data latching clock signals.

4. The system as claimed in claim 1 wherein the one or more common data ports comprises one of 1 bit, 2 bits, 4 bits, 8 bits, and 16 bits.

5. The system as claimed in claim 1 wherein the external reference voltage is set to a predetermined voltage level.

6. The system as claimed in claim 1 wherein the external reference voltage is set to half of the common data signal's high logic level.

7. The system as claimed in claim 1 wherein the first and second input signals and the common data signals are terminated signals.

8. The system as claimed in claim 1 wherein the first and second input signals and the common data signals are SSTL signals.

9. The system as claimed in claim 1 wherein the at least one non-volatile memory device is a flash memory device.

10. The system as claimed in claim 1 wherein the at least one non-volatile memory device is a NAND flash memory device.

11. The system as claimed in claim 1 wherein the system includes at least one DRAM memory device communicatively coupled to the memory controller for caching operation.

12. A non-volatile memory device comprising:
at least two non-volatile memory banks;
a chip enable input port configured to receive a chip enable signal for enabling the non-volatile memory device;
a first input port configured to receive a first input signal;
a second input port configured to receive a second input signal, the second input signal being complementary to the first input signal;
a reference voltage input port configured to receive an external reference voltage;
a plurality of common data ports configured to receive common data signals carrying command data and at least one of address data and write data, the write data to be latched in synchronization with both rising and falling edges of at least the first input signal and to be programmed into one of the at least two non-volatile memory banks addressable by the address data;
a first configurable input buffer configured to be able to switch from a single ended signaling configuration to a differential signaling configuration, the differential signaling configuration configured to utilize the first input signal and the second input signal as differential signals, and the single ended signaling configuration configured to utilize one of the first input signal and the second input signal as a single ended signal;
a second configurable input buffer configured to be able to utilize the external reference voltage for determining a logic level of the common data signals; and
a configurable output buffer configured to set an output drive strength to provide data from one of the at least two non-volatile memory banks in response to a read command from the memory controller.

13. The non-volatile memory device as claimed in claim 12 wherein the first and second input signals are a positive clock input signal and a negative clock input signal respectively.

14. The non-volatile memory device as claimed in claim 12 wherein the first and second input signals are data latching clock signals.

15. The non-volatile memory device as claimed in claimed 12 wherein the one or more common data ports comprises one of the 1 bit, 2 bits, 4 bits, 8 bits, and 16 bits.

16. The non-volatile memory device as claimed in claim 12 wherein the external reference voltage is set to a predetermined voltage level.

17. The non-volatile memory device as claimed in claim 12 wherein the external reference voltage is set to half of the common data signal's high logic level.

18. The non-volatile memory device as claimed in claim 12 wherein the first and second input signals and the common data signals are terminated signals.

19. The non-volatile memory device as claimed in claim 12 wherein the first and second input signals and the common data signals are SSTL signals.

20. The non-volatile memory device as claimed in claim 12 wherein the non-volatile memory device is a flash memory device.

21. The non-volatile memory device as claimed in claim 12 wherein the non-volatile memory device is a NAND flash memory device.

Assignees

• Conversant Intellectual Property Man Inc

Inventors

• Gillingham Peter B
• Allan Graham

Classifications

• G11C7/225

  Clock input buffers · CPC title

• G11C16/32 Primary

  Timing circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title