SRAM module and writing control method thereof

Patent metadata

Field	Value
Publication number	US-9870817-B2
Application number	US-201514729853-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Feb 6, 2015
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A SRAM module and a writing control method of the SRAM module are disclosed. The writing control method of the SRAM module is applied to a SRAM module that includes a plurality of memory cells and a bit line. The method includes: providing a first voltage as a supply voltage of the plurality of memory cells during a data retention time; decreasing a first voltage level corresponding to the data retention time of the memory cells to a second voltage level by discharging the memory cells; and performing a write process to the memory cells through the bit line. The discharge time from the first voltage level to the second voltage level is related to the number of the memory cells.

First claim

What is claimed is:

1. An SRAM module having a plurality of memory cells, comprising:
a bit line, coupled to the memory cells, for transmitting a write data; a detecting unit, coupled to the memory cells, for generating a control signal by detecting a voltage change on the memory cells: a capacitor, coupled to the bit line; and
a charge unit, coupled to the detecting unit and the capacitor, for charging the capacitor according to the control signal;
wherein, after the capacitor is charged, a voltage difference at the two ends of the capacitor is used to cause a voltage drop on the bit line, and
wherein the memory cells from an equivalent capacitor, which has a terminal voltage, and the detecting unit changes a level of the control signal by detecting a change in the terminal voltage so as to activate the charge unit to charge the capacitor.

2. The SRAM module of claim 1 further comprising:
a simulation memory unit having a characteristic value related to the number of the memory cells;
wherein, the detecting unit is coupled to the simulation memory unit for generating the control signal according to the characteristic value.

3. The SRAM module of claim 2 , wherein the simulation memory unit forms an equivalent capacitor and the characteristic value is a capacitance of the equivalent capacitor.

4. The SRAM module of claim 3 , wherein a charge time of the capacitor is proportional to the capacitance.

5. The SRAM module of claim 2 , wherein the simulation memory unit comprises a plurality of dummy memory cells, and the number of the dummy memory cells is proportional to the number of memory cells connected to the bit line.

6. The SRAM module of claim 1 further comprising:
a reset unit, coupled to the capacitor, for coupling an end of the capacitor to ground according to a reset signal in order that the voltage drop is generated at the other end of the capacitor.

7. The SRAM module of claim 6 , wherein when the reset unit is activated by the reset signal, a voltage level of the end of the capacitor is pulled down to the ground, which makes the voltage difference on the capacitor generate a negative voltage on the bit line.

8. The SRAM module of claim 1 , wherein the detecting unit comprises a discharge unit, which discharges a voltage of the memory cells according to an enable signal.

9. The SRAM module of claim 8 , wherein the discharge unit discharges the voltage of the memory cells to activate the charge unit to charge the capacitor.

10. The SRAM module of claim 1 , wherein the capacitor is a NMOS capacitor or a PMOS capacitor.

11. A method of controlling an SRAM module having a plurality of memory cells, comprising:
generating a control signal by detecting a voltage change on the memory cells;
charging a capacitor that is coupled to a bit line according to the control signal, wherein the bit line is further coupled to the memory cells; and using a voltage difference at two ends of the capacitor to cause a voltage drop on the bit line after the capacitor is charged, and
wherein the memory cells form an equivalent capacitor having a terminal voltage, and the step of generating the control signal comprises:
changing a level of the control signal by detecting a change in the terminal voltage so as to charge the capacitor.

12. The method of claim 11 , wherein the SRAM module further comprises a simulation memory unit having a characteristic value related to the number of the memory cells, and the step of generating the control signal comprises: generating the control signal according to the characteristic value.

13. The method of claim 12 , wherein the simulation memory unit forms an equivalent capacitor and the characteristic value is a capacitance of the equivalent capacitor.

14. The method of claim 13 , wherein the step of charging the capacitor comprises:
charging the capacitor according to a charge time that is proportional to the capacitance.

15. The method of claim 12 , wherein the simulation memory unit comprises a plurality of dummy memory cells, and the number of the dummy memory cells is proportional to the number of memory cells connected to the bit line.

16. The method of claim 11 further comprising:
coupling an end of the capacitor to the ground according to a reset signal in order that the voltage drop is generated at the other end of the capacitor.

17. The method of claim 11 , further comprising:
discharging a voltage of the memory cells according to an enable signal.

18. The method of claim 17 , wherein the step of discharging the voltage of the memory cells comprises:
discharging the voltage of the memory cells to activate the charge unit to charge the capacitor.

19. The method of claim 16 , wherein when coupling the end of the capacitor to the ground, a voltage level of the end of the capacitor is pulled down to the ground, which makes the voltage difference on the capacitor generate a negative voltage on the bit line.

20. The method of claim 11 , wherein the capacitor is a NMOS capacitor or a PMOS capacitor.

Assignees

• M31 Tech Corp

Inventors

• Lien Nan-Chun
• Yu David C

Classifications

• G11C11/419 Primary

  Read-write [R-W] circuits · CPC title