Memory device write circuitry

Patent metadata

Field	Value
Publication number	US-10535396-B2
Application number	US-201816049576-A
Country	US
Kind code	B2
Filing date	Jul 30, 2018
Priority date	Dec 27, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.

First claim

What is claimed is:

1. A memory device comprising:
a main input-output line;
driving circuitry configured to generate a main input-output signal on the main input-output line; and
a plurality of sensing amplifiers coupled to the main input-output line and each configured to be written to or transmit data over the main input-output line, wherein each sensing amplifier comprises:
a local data line, wherein the local data line and the main input-output line are coupled to different terminals of a pull-down transistor, wherein at least one of the terminals is a gate terminal of the transistor;
local data line generation circuitry configured to generate a local data signal on the local data line; and
a plurality of local sensing amplifiers coupled to the local data line generation circuitry via the local data line.

2. The memory device of claim 1 comprising a main input-output false line that is complementary to the main input-output line, wherein the main input-output false line is generated by the driving circuitry.

3. The memory device of claim 2 , wherein the local data line generation circuitry generates a local false line using the main input-output false line, wherein the local false line is complementary to the local data line.

4. The memory device of claim 1 , wherein the local data line generation circuitry comprises the pull-down transistor that is configured to receive the main input-output line at a gate of the pull-down transistor and selectively couple the local data line to a low voltage.

5. The memory device of claim 4 , wherein the local data line generation circuitry comprises a gate transistor in series with the pull-down transistor, wherein the gate transistor is configured to receive a write enable signal to control whether the pull-down transistor coupling to the low voltage is completed.

6. The memory device of claim 5 , wherein the local data line comprises a pair of cross-p-channel transistors that are configured to respond to a connection of the local data line to the low voltage by connecting a local false line to a high voltage and to respond to a connection of the local false line to the low voltage through the complementary pull-down transistor by connecting the local data line to a high voltage.

7. The memory device of claim 1 , wherein the driving circuitry is configured to set the main input-output signal based at least in part on a write enable signal.

8. The memory device of claim 1 , wherein the driving circuitry is configured to set the main input-output signal based on a data signal.

9. The memory device of claim 1 , wherein the memory device comprises a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device.

10. A semiconductor device comprising:
a main data line;
a main false line, wherein the main false line is complementary to the main data line;
driving circuitry configured to generate a main data line signal on the main data line and a main false signal on the main false line; and
a plurality of sensing amplifiers coupled to the main data line and the main false line, wherein each of the plurality of sensing amplifiers is configured to be written to or transmit data over the main data line and the main false line, wherein each sensing amplifier comprises:
a local data line;
a local false line that is complementary to the local data line;
local data line generation circuitry configured to generate:
a local data signal on the local data line; and
a local false signal on the local false line, wherein the local data line generation circuitry comprises a pull-down transistor that is configured to receive the main input-output line at a gate terminal of the pull-down transistor and to selectively couple the local data line to a low voltage using a non-gate terminal of the pull-down transistor coupled to the local data line; and

a plurality of local sensing amplifiers coupled to the local data line generation circuitry via the local data line and the local false line.

11. The semiconductor device of claim 10 , wherein the local data line generation circuitry comprises:
a data pull-down transistor configured to receive the main data line at a gate of the data pull-down transistor to control whether the local data line is coupled to a low voltage; and
a complementary pull-down transistor configured to receive the main false line at a gate of the complementary pull-down transistor to control whether the local false line is coupled to the low voltage using a non-gate terminal of the complementary pull-down transistor coupled to local false line.

12. The semiconductor device of claim 11 , wherein the local data line generation circuitry comprises:
a first gate transistor to block connection of the local data line to the low voltage absent receiving an assertion of a write enable signal at a gate of the first gate transistor; and
a second gate transistor to block connection of the local false line to the low voltage absent receiving the assertion of the write enable signal at a gate of the first gate transistor.

13. The semiconductor device of claim 12 , wherein the driving circuitry is configured to use the write enable signal to modify the main data line and the main false line.

14. The semiconductor device of claim 11 , wherein the driving circuitry is configured to generate the main data line and the main false line in two states:
a first state with the main data line driven to a first voltage and the main false line driven to a second voltage; and
a second state with the main data line driven to the second voltage and the main false line driven to the first voltage.

15. The semiconductor device of claim 14 , wherein the first voltage comprises a voltage to overcome a threshold voltage of the data pull-down transistor or the complementary pull-down transistor.

16. The semiconductor device of claim 14 , wherein the first voltage comprises a threshold voltage of the data pull-down transistor or the complementary pull-down transistor plus an additional set cushion.

17. The semiconductor device of claim 10 , wherein each of the plurality of sensing amplifiers comprises:
a plurality of first local gate transistors each corresponding to a respective local sensing amplifier of the plurality of local sensing amplifiers, wherein each of the plurality of first local gate transistors are configured to receive a respective column selector signal at its gate to control whether the respective local sensing amplifier receives the local data line; and
a plurality of second local gate transistors each corresponding to a respective local sensing amplifier of the plurality of local sensing amplifiers, wherein each of the plurality of second local gate transistors are configured to receive a respective column selector signal at its gate to control whether the respective local sensing amplifier receives the local false line.

18. A method comprising
receiving a main data line from driving circuitry;
receiving a main bar line from the driving circuitry;
locally generating a local data line at local data line generation circuitry of a sensing amplifier of a plurality of sensing amplifiers coupled to the main data line, wherein locally generating the local data line comprises generating the local data line based at least in part on the local data line and the main input-output line being coupled to different terminals of a pull-down transistor, wherein at least one of the different terminals is a gate terminal of the transistor;
locally generating a local bar line at the local data li

Assignees

• Micron Technology Inc

Inventors

• Venkata Harish N

Classifications

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C7/1096

  Write circuits, e.g. I/O line write drivers · CPC title

• G11C7/08

  Control thereof · CPC title

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title