Semiconductor device and a method for fabricating the same

Patent metadata

Field	Value
Publication number	US-12166038-B2
Application number	US-202318224487-A
Country	US
Kind code	B2
Filing date	Jul 20, 2023
Priority date	Feb 10, 2016
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of n-type field effect transistors (NFETs) having three different threshold voltages; and
a plurality of p-type FETs (PFETs) having three different threshold voltages, wherein:
the plurality of NFETs include a first NFET having a first gate structure including a first work function adjustment material (WFM) layer disposed directly on a first barrier layer disposed over a first gate dielectric layer,
the plurality of PFETs include a first PFET having a second gate structure including a second WFM layer disposed directly on a second barrier layer disposed over a second gate dielectric layer,
the first WFM layer includes a first TiN layer disposed on the first barrier layer and a first aluminum containing layer disposed on the first TiN layer,
the second WFM layer includes a second TiN layer disposed on the second barrier layer and a second aluminum containing layer disposed over the second TiN layer, and
the first NFET has a second lowest threshold voltage in an absolute value among the plurality of NFETs, and the first PFET has a second lowest threshold voltage in an absolute value among the plurality of PFETs.

2. The semiconductor device of claim 1 , wherein each of the first and second aluminum containing layers includes TiAlC.

3. The semiconductor device of claim 2 , wherein:
the first gate structure further includes a first adhesion layer disposed directly on the first WFM layer and a first metal layer disposed on the first adhesion layer, and
the second gate structure further includes a second adhesion layer disposed directly on the second WFM layer and a second metal layer disposed on the second adhesion layer.

4. The semiconductor device of claim 3 , wherein:
the first and second adhesion layers include a TiN layer, and
the first and second metal layers include a W layer.

5. The semiconductor device of claim 1 , wherein a thickness of each of the first and second aluminum containing layers is in a range from 0.5 nm to 10 nm.

6. The semiconductor device of claim 1 , wherein a thickness of the first TiN layer is smaller than a thickness of the second TiN layer.

7. The semiconductor device of claim 1 , wherein each of the first and second barrier layers includes a TaN layer.

8. A semiconductor device comprising:
a plurality of p-type field effect transistors (PFETs) having three different threshold voltages, wherein:
each of the plurality of PFETs includes a gate structure including a first barrier layer disposed over a first gate dielectric layer, and a TiN layer and an aluminum containing layer disposed over the TiN layer, and
a first PFET among the plurality of PFETs has a highest threshold voltage in an absolute value and a thickness of the TiN layer of the first PFET is smallest among the plurality of PFETs.

9. The semiconductor device of claim 8 , wherein the aluminum containing material is TiAlC.

10. The semiconductor device of claim 8 , wherein:
the gate structure further includes an adhesion layer disposed directly on the aluminum containing layer and a metal layer disposed on the first adhesion layer.

11. The semiconductor device of claim 10 , wherein:
the adhesion layers includes a TiN layer, and
the metal layers includes a W layer.

12. The semiconductor device of claim 8 , wherein a thickness of the aluminum containing layer is in a range from 0.5 nm to 10 nm.

13. The semiconductor device of claim 8 , wherein a thickness of the TiN layer in the first PFET is 2.0 nm to 3.5 nm.

14. The semiconductor device of claim 8 , wherein the first barrier layer includes a TaN layer.

15. A semiconductor device, comprising:
a first n-channel FET (NEFT) including a first gate structure and having a threshold voltage Vn 1 ;
a second NFET including a second gate structure and having a threshold voltage Vn 2 ; and
a third NFET including a third gate structure and having a threshold voltage Vn 3 , wherein:
Vn 1 <Vn 2 <Vn 3 in absolute values,
the first gate structure includes a first work function adjustment material (WFM) layer, the second gate structure includes a second WFM layer, and the third gate structure includes a third WFM layer,
each of the second and third WFM layers includes a TiN layer,
the first WFM layer does not include a TiN layer, and
each of the first, second and third WFM layers includes an aluminum containing layer.

16. The semiconductor device of claim 15 , wherein a thickness of the TiN of the second WFM layer is smaller than a thickness of the third WFM layer.

17. The semiconductor device of claim 16 , wherein the TiN layer is disposed below the Al containing layer.

18. The semiconductor device of claim 15 , wherein the aluminum containing layer includes TiAlC.

19. The semiconductor device of claim 15 , wherein:
the first, second and third WFM layers are formed over a first conductive layer disposed over a gate dielectric layer, and
a second conductive layer is disposed over each of the first, second and third WFM layers with a third conductive layer interposed therebetween.

20. The semiconductor device of claim 19 , wherein:
the first conductive layer is a TaN layer,
the second conductive layer includes a W layer, and
the third conductive layer includes a TiN layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liao Shun-Jang
• Liao Chia-Chun
• Wang Shu-Hui
• Chang Shih-Hsun

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title