Integrated circuits with varying gate structures and fabrication methods

Patent metadata

Field	Value
Publication number	US-9576952-B2
Application number	US-201414188778-A
Country	US
Kind code	B2
Filing date	Feb 25, 2014
Priority date	Feb 25, 2014
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).

First claim

What is claimed is:

1. A device comprising:
an integrated circuit, the integrated circuit comprising:
a varying gate structure disposed over a substrate structure, the varying gate structure comprising a first gate stack in a first region of the substrate structure, a second gate stack in a second region of the substrate structure, a third gate stack in a third region of the substrate structure, and a fourth gate stack in a fourth region of the substrate structure, wherein the first gate stack, second gate stack, third gate stack and fourth gate stack are different gate stacks;
a first field-effect transistor in the first region of the substrate structure, the first field-effect transistor comprising the first gate stack of the varying gate structure and having a first threshold voltage; and
a second field-effect transistor in the second region of the substrate structure, the second field-effect transistor comprising the second gate stack of the varying gate structure and having a second threshold voltage, wherein the first threshold voltage is different from the second threshold voltage,
a third field-effect transistor in the third region of the substrate structure, the third field-effect transistor comprising the first gate stack of the varying gate structure and having a third threshold voltage different than the first and second threshold voltages; and
a fourth field-effect transistor in the fourth region of the substrate structure, the fourth field-effect transistor comprising the fourth gate stack of the varying gate structure and having a fourth threshold voltage that is different from the first, second and third threshold voltages,

wherein the first gate stack and the second gate stack of the varying gate structure comprises a gate dielectric layer, a first cap layer overlying the gate dielectric layer, a second cap layer overlying the first cap layer, a first work-function layer overlying the second cap layer, and a metal layer overlying the second work function layer,
wherein the second cap layer has a first thickness in the first gate stack and a second thickness in the second gate stack that is different from the first thickness,
wherein the first gate stack and the second gate stack of the varying gate structure comprises the layers of the first and second gate stacks and a second work function layer positioned between the second conductive cap layer and the first work function layer, and
wherein the second cap layer has the first thickness in the third gate stack and the second thickness at the fourth gate stack, and
wherein the second work function layer has a first thickness in the third gate stack and a second thickness in the fourth gate stack that is different from the first thickness.

2. The device of claim 1 , wherein the first work function layer has a third thickness in the first region and a fourth thickness in the second region that is different from the third thickness.

3. The device of claim 2 , wherein the first thickness is less than the second thickness, and the third thickness is greater than the fourth thickness.

4. The device of claim 1 , wherein a portion of the varying gate structure extends from the first field-effect transistor to the second field-effect transistor.

5. The device of claim 1 , wherein the first threshold voltage is between 80 and 120 millivolts greater than the second threshold voltage.

6. The device of claim 1 , wherein the substrate structure comprises a first fin extending over the first and second regions of the substrate structure and a second fin extending over the second third and fourth regions of the substrate structure, and the varying gate structure is conformally disposed over the first fin and the second fin.

7. The method of claim 6 , wherein a portion of the varying gate structure extends from the first field-effect transistor to the second field-effect transistor.

8. The device of claim 6 , wherein the first fin and the second fin are a common fin.

9. The device of claim 1 , wherein the first gate stack, second gate stack, third gate stack and fourth gate stack of the varying gate structure further comprise an interfacial layer disposed between the substrate and the dielectric layer.

10. The device of claim 1 , wherein the first cap layer has substantially the same thickness in the first gate stack, second gate stack, third gate stack and fourth gate stack.

11. The device of claim 10 , wherein the thickness of the first cap layer in the first gate stack, second gate stack, third gate stack and fourth gate stack is between about 10 Å and about 15 Å.

12. The device of claim 1 , wherein the first thickness and the second thickness of the second cap layer is between 10 Å and 15 Å.

13. The device of claim 1 , wherein the first cap layer comprises TiN or TaN.

14. The device of claim 1 , wherein the second cap layer comprises TiN or TaN.

15. The device of claim 2 , wherein the gate dielectric layer is proximate to the substrate structure.

16. The device of claim 1 , wherein the first gate stack, the second gate stack, the third gate stack and the fourth gate stack are formed over a fin formed on the substrate structure.

17. The device of claim 16 , wherein the first gate stack, the second gate stack, the third gate stack and the fourth gate stack are formed on respective pairs of spaced spacers formed on the fin.

18. The device of claim 16 , wherein the inner side walls of the pairs of spacers and the respective portions of the fin extending between the spacers of the pairs of spacers form channels, and wherein the first gate stack, the second gate stack, the third gate stack and the fourth gate stack are formed over the channel.

19. The device of claim 18 , wherein an oxide layer extends on the respective portions of the fin extending between the spacers of the pairs of spacers, wherein the dielectric layer is formed on the inner side walls of the pairs of spacers and the oxide layer at the first gate stack, the second gate stack, the third gate stack and the fourth gate stack.

20. The device of claim 19 , wherein the first gate stack and the second gate stack are formed over a first fin formed on the substrate structure, and the third gate stack and the fourth gate stack are formed over a second fin formed on the substrate structure.

Assignees

• Globalfoundries Inc

Inventors

• Joshi Manoj
• Eller Manfred
• Carter Richard J
• Samavedam Srikanth Balaji

Classifications

• H01L27/0924

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L27/0922

  Electricity · mapped topic

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic